公开(公告)号：US20170070214A1

公开(公告)日：2017-03-09

申请号：US15253270

申请日：2016-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SAN-HA KIM ,  MIN-SU KIM ,  MATTHEW BERZINS

IPC: H03K3/012 ,  H03K3/037

CPC classification number: H03K3/012 ,  H03K3/356121

Abstract: A semiconductor circuit includes a first circuit and a second circuit. The first circuit determines a logic level of a second node and a logic level of a third node, on the basis of a logic level of input data, a logic level of a clock signal, and a logic level of a first node. The second circuit determines the logic level of the first node, on the basis of the logic level of the clock signal, the logic level of the second node and the logic level of the third node. The first circuit comprises a sub-circuit and a first transistor. The first circuit determines the logic level of the second node, on the basis of the logic level of the input data and the logic level of the first node. The first transistor is gated to the logic level of the clock signal to connect the third node with the second node.

Abstract translation: 半导体电路包括第一电路和第二电路。 第一电路基于输入数据的逻辑电平，时钟信号的逻辑电平和第一节点的逻辑电平来确定第二节点的逻辑电平和第三节点的逻辑电平。 第二电路基于时钟信号的逻辑电平来确定第一节点的逻辑电平，第二节点的逻辑电平和第三节点的逻辑电平。 第一电路包括子电路和第一晶体管。 第一电路基于输入数据的逻辑电平和第一节点的逻辑电平来确定第二节点的逻辑电平。 第一晶体管被选通到时钟信号的逻辑电平以将第三节点与第二节点连接。

公开(公告)号：US20170292993A1

公开(公告)日：2017-10-12

申请号：US15479310

申请日：2017-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DOO-SEOK YOON ,  MIN-SU KIM ,  CHUNG-HEE KIM ,  DAE-SEONG LEE ,  HYUN LEE ,  MATTHEW BERZINS ,  JAMES LIM

IPC: G01R31/3177 ,  G01R31/317 ,  H03K3/037

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31725 ,  G01R31/318541 ,  H03K3/0372

Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.

公开(公告)号：US20170016955A1

公开(公告)日：2017-01-19

申请号：US15281998

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MIN-SU KIM ,  MATTHEW BERZINS ,  JONG-WOO KIM

IPC: G01R31/3177 ,  H03K19/21 ,  G01R31/317 ,  H03K3/037

CPC classification number: G01R31/3177 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318541 ,  H03K3/0372 ,  H03K3/35625 ,  H03K19/21

Abstract: A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.

Abstract translation: 多位触发器包括共享时钟信号的多个多位触发器块。 多位触发器块中的每一个包括单个反相器和多个触发器。 单个反相器通过反相时钟信号产生反相时钟信号。 每个触发器包括主锁存部分和从锁存器部分，并且基于时钟信号和反相时钟信号操作主锁存器部分和从锁存器部分。 这里，触发器在时钟信号的上升沿被触发。 因此，作为主从触发器操作的多位触发器可以最小化（或降低）发送时钟信号的时钟通路中发生的功耗。