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11.
公开(公告)号:US20190018597A1
公开(公告)日:2019-01-17
申请号:US15870390
申请日:2018-01-12
Applicant: SanDisk Technologies LLC
Inventor: Yuheng Zhang , Gordon Yee , Yibo Yin , Tz-Yi Liu
IPC: G06F3/06
Abstract: A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.
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公开(公告)号:US20180357123A1
公开(公告)日:2018-12-13
申请号:US15934565
申请日:2018-03-23
Applicant: SanDisk Technologies LLC
Inventor: Yibo Yin , Henry Zhang , Po-Shen Lai , Vijay Chinchole , Spyridon Georgakis , Yan Li , Hiroyuki Mizukoshi , Toru Miwa , Jayesh Pakhale , Tz-Yi Liu
IPC: G06F11/10
CPC classification number: G06F11/1016 , G06F11/1064
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
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