公开(公告)号：US09837152B2

公开(公告)日：2017-12-05

申请号：US15392852

申请日：2016-12-28

Applicant: SanDisk Technologies LLC

Inventor： Gopinath Balakrishnan ,  Yibo Yin ,  Tianhong Yan

IPC: G11C8/00 ,  G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/12 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0088

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

公开(公告)号：US20190018597A1

公开(公告)日：2019-01-17

申请号：US15870390

申请日：2018-01-12

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Gordon Yee ,  Yibo Yin ,  Tz-Yi Liu

IPC: G06F3/06

Abstract: A sequencer circuit is configured to generate control signals for on-die memory control circuitry. The control signals may include memory operation pulses for implementing operations on selected non-volatile memory cells embodied within the same die as the sequencer (and other on-die memory control circuitry). The timing, configuration, and/or duration of the memory control signals are defined in configuration data, which can be modified after the design and/or fabrication of the die and/or on-die memory circuitry. As such, the timing, configuration, and/or duration of the memory control signals generated by the sequencer may be manipulated after the design and/or fabrication of the die, sequencer, and other on-die memory control circuitry.

公开(公告)号：US20170110189A1

公开(公告)日：2017-04-20

申请号：US15392852

申请日：2016-12-28

Applicant: SanDisk Technologies LLC

Inventor： Gopinath Balakrishnan ,  Yibo Yin ,  Tianhong Yan

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C8/12 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0088

Abstract: Independent sense amplifier addressing provides separate column addresses to individual sense amplifier groups within a single bay during one column address cycle. A memory system determines whether the individual memory cells or bits of a column at a bay can be skipped. For each sense amplifier group having at least one memory cell (or bit) that needs to be programmed, the system determines for the first column address whether the memory cell can be skipped. If a bit or memory cell having a first column address from the sense amplifier group can be skipped, the system determines a next bit having a column address from the group that needs to be programmed. The system groups the next column address for programming during the first column address cycle. The system can program a different column address for different sense amplifier groups within the bay during a single column address cycle.

公开(公告)号：US20180357123A1

公开(公告)日：2018-12-13

申请号：US15934565

申请日：2018-03-23

Applicant: SanDisk Technologies LLC

Inventor： Yibo Yin ,  Henry Zhang ,  Po-Shen Lai ,  Vijay Chinchole ,  Spyridon Georgakis ,  Yan Li ,  Hiroyuki Mizukoshi ,  Toru Miwa ,  Jayesh Pakhale ,  Tz-Yi Liu

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1064

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.