公开(公告)号：US20210175172A1

公开(公告)日：2021-06-10

申请号：US17180094

申请日：2021-02-19

Applicant: SOCIONEXT INC.

Inventor： Isaya SOBUE ,  Hidetoshi TANAKA ,  Mai TSUKAMOTO

IPC: H01L23/528 ,  H01L27/02

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

公开(公告)号：US20180337231A1

公开(公告)日：2018-11-22

申请号：US15972949

申请日：2018-05-07

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi TANAKA

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.