公开(公告)号：US20210184035A1

公开(公告)日：2021-06-17

申请号：US17187179

申请日：2021-02-26

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA ,  Isaya SOBUE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L23/522 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate and a resistance element provided above the semiconductor substrate, the resistance element includes a conductive pattern using a gate electrode film formed simultaneously with a gate electrode film arranged on a side surface of a semiconductor nanowire of a VNW transistor, and there is fabricated the semiconductor device that includes the VNW transistor having the semiconductor nanowire and the resistance element having sufficient electrical resistance.

公开(公告)号：US20220077137A1

公开(公告)日：2022-03-10

申请号：US17467069

申请日：2021-09-03

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA ,  Mai Tsukamoto

IPC: H01L27/02 ,  H01L23/522

Abstract: A semiconductor device includes a pad portion, a protection circuit, N wiring layers, and conductive vias connecting adjacent wiring layers, wherein, in a plan view, the semiconductor device includes a first area, a second area, and a third area, wherein the N wiring layers are provided to extend over the first area, the second area, and the third area, wherein a first wiring layer on a side of the pad portion is connected to the pad portion in the first area, and wherein an N-th wiring layer on a side of the protection circuit is connected to the protection circuit in the second area, and in the second area and the third area, where a total cross-sectional area of i-th conductive vias connecting an i-th wiring layer and an (i+1)-th wiring layer is denoted as Si, S1 is smaller than Sj for any j (j being 2 or more).

公开(公告)号：US20240213770A1

公开(公告)日：2024-06-27

申请号：US18596231

申请日：2024-03-05

Applicant: Socionext Inc.

Inventor： Hidetoshi TANAKA ,  Yuko NAGAI

IPC: H02H9/04 ,  H01L23/522

CPC classification number: H02H9/046 ,  H01L23/5228

Abstract: An IO cell includes an output circuit having an ESD protection diode, a protective resistance, and an output transistor. The protective resistance is constituted by a plurality of resistor elements formed in a first interconnect layer that is formed in an interconnect process (back end of line (BEOL)). The resistor elements are connected to interconnects formed in a second interconnect layer through vias. In the second interconnect layer, first power supply lines supplying first power are formed above the ESD protection diode. The first power supply lines have overlaps at positions in the X direction with the resistor elements.

公开(公告)号：US20240038757A1

公开(公告)日：2024-02-01

申请号：US18477145

申请日：2023-09-28

Applicant: Socionext Inc.

Inventor： Hidetoshi TANAKA

IPC: H01L27/02 ,  H01L23/522

CPC classification number: H01L27/0248 ,  H01L23/5228

Abstract: In a semiconductor integrated circuit device, first and second interconnects extending in the X direction are formed in a metal interconnect layer. The first and second interconnects are placed on the opposite sides of each resistor element in the X direction and connected to the resistor element. The first interconnect is connected to PAD, and a third interconnect is connected to VSS. In an ESD protection diode, an anode and a cathode are formed alternately in the Y direction. The resistor element and the first and second interconnects overlap the cathode of the ESD protection diode, and the third interconnect overlaps the anode of the ESD protection diode, in planar view.

公开(公告)号：US20200044017A1

公开(公告)日：2020-02-06

申请号：US16599907

申请日：2019-10-11

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring formed on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.

公开(公告)号：US20190393302A1

公开(公告)日：2019-12-26

申请号：US16563670

申请日：2019-09-06

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi TANAKA

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/088

Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.

公开(公告)号：US20180342575A1

公开(公告)日：2018-11-29

申请号：US15982775

申请日：2018-05-17

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi TANAKA

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02

Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring faulted on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.

公开(公告)号：US20250151412A1

公开(公告)日：2025-05-08

申请号：US19018857

申请日：2025-01-13

Applicant: Socionext Inc.

Inventor： Hidetoshi TANAKA

IPC: H10D89/60 ,  H01L23/522 ,  H10D1/47

Abstract: An IO cell includes an output circuit having a protective resistance. The protective resistance is constituted by a plurality of resistor elements formed in a first interconnect layer that is formed in the back end of line (BEOL). In an interconnect layer located below the first interconnect layer, interconnects that are each a power supply line or a signal line extend in the X direction and are adjacent to each other in the Y direction. The interconnects do not overlap any of the resistor elements in planar view, and at least one resistor element is placed between the interconnects.

公开(公告)号：US20240072058A1

公开(公告)日：2024-02-29

申请号：US18489440

申请日：2023-10-18

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hidetoshi TANAKA

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: In a semiconductor integrated circuit device, an output circuit includes a first transistor connected between VSS and an output terminal. A first power line supplying VSS is formed in a buried interconnect layer, and above the buried interconnect layer, a second power line supplying VSS is formed in an M1 interconnect layer and a third power line connected to the second power line is formed in an M2 interconnect layer. A first output interconnect is formed in the M1 interconnect layer, and a second output interconnect connected to the first output interconnect is formed in the M2 interconnect layer.

公开(公告)号：US20220262787A1

公开(公告)日：2022-08-18

申请号：US17735052

申请日：2022-05-02

Applicant: Socionext Inc.

Inventor： Hidetoshi TANAKA

IPC: H01L27/02 ,  H02H9/04

Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.