公开(公告)号：US20220130478A1

公开(公告)日：2022-04-28

申请号：US17524535

申请日：2021-11-11

Applicant: SOCIONEXT INC.

Inventor： Yasumitsu SAKAI ,  Shinichi MORIWAKI

IPC: G11C17/12 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C5/06

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.