公开(公告)号：US10014834B1

公开(公告)日：2018-07-03

申请号：US15393550

申请日：2016-12-29

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal ,  Denis Cottin ,  Patrik Arno ,  Nicolas Marty

IPC: H03F3/45 ,  H03F1/32

Abstract: An embodiment circuit includes a first voltage divider coupled between a first voltage level and a ground potential. The circuit further includes an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider. The circuit further includes a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.

公开(公告)号：US20240110826A1

公开(公告)日：2024-04-04

申请号：US17955056

申请日：2022-09-28

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal

IPC: G01J1/42 ,  G01J1/44

CPC classification number: G01J1/4204 ,  G01J1/44 ,  G01J2001/446 ,  H03F3/45071

Abstract: A circuit can be used for reading out a light sensor. The circuit includes an operational amplifier. A first capacitor has a first electrode coupled to an inverting input of the operational amplifier and a second electrode coupled to a non-inverting output of the operational amplifier. A compensation circuit is coupled between the operational amplifier and the first capacitor. A preset circuit has an input coupled to a first voltage node and an output coupled to the first capacitor. The first voltage node configured to carry a first voltage equal to a preset voltage multiplied by a coefficient.

公开(公告)号：US20230327621A1

公开(公告)日：2023-10-12

申请号：US18189665

申请日：2023-03-24

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal

IPC: H03F3/45 ,  H03F1/02

CPC classification number: H03F3/45179 ,  H03F1/0205

Abstract: In an embodiment a device includes an input node configured to receive a first current, an output node configured to provide a second current determined by the first current, a first resistor having a first terminal connected to the input node and a second terminal coupled to a first node configured to receive a first supply voltage, a first MOS transistor having a source connected to the first node and a drain coupled to the output node of the device, a second resistor having a first terminal connected to a gate of the first MOS transistor, a biasing circuit configured to provide a biasing voltage on a second terminal of the second resistor and a first capacitor connected between the input node and the gate of the first MOS transistor.

公开(公告)号：US10236842B2

公开(公告)日：2019-03-19

申请号：US15393485

申请日：2016-12-29

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Vratislav Michal ,  Michel Ayraud

IPC: H03F3/45 ,  H03F1/02 ,  G01R1/30 ,  G01R31/36

Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.

公开(公告)号：US09892877B2

公开(公告)日：2018-02-13

申请号：US14657991

申请日：2015-03-13

Applicant: STMicroelectronics (Alps) SAS

Inventor： Vratislav Michal ,  Denis Cottin

IPC: H01H47/00 ,  H03K17/16 ,  H03K17/30

CPC classification number: H01H47/00 ,  H03K17/167 ,  H03K17/30 ,  H03K2017/307 ,  Y10T307/76

Abstract: A circuit including: a plurality of first switches connected in parallel between a first terminal and a second terminal; and a control circuit capable of implementing the following steps at each period of a clock signal: comparing the voltage between the first and second terminals with a reference voltage; if the voltage between the first and second terminals is greater than the reference voltage, turning on one of the first switches without modifying the state of the other switches; and if the voltage between the first and second terminals is smaller than the reference voltage, turning off one of the first switches without modifying the state of the other switches.