公开(公告)号：US20150270947A1

公开(公告)日：2015-09-24

申请号：US14221162

申请日：2014-03-20

Applicant: STMicroelectronics International N.V.

Inventor： Anurag TIWARI ,  Kallol CHATTERJEE

IPC: H04L7/027 ,  H04L7/033 ,  H03L7/087

CPC classification number: H04L7/027 ,  H03L7/087 ,  H03L7/22 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/0332

Abstract: A circuit and method for referenceless CDR with improved efficiency and jitter tolerance by using an additional loop for frequency detection. Such an improved circuit includes a frequency detector for identifying whether an initial recovered clock signal is faster or slower than the actual bit rate of the received data stream. The frequency detector provides a jitter tolerance of +/−0.5 UI and uses significantly fewer components that other conventional frequency detectors. Having fewer components, significantly less power is also consumed. In an embodiment, the FD uses only four flip-flops, two AND gates, and one delay circuit. Having fewer components also uses less die space in integrated circuits. Having high jitter tolerance and fewer components is an improvement over conventional referenceless CDR circuits.

Abstract translation: 一种用于无参考CDR的电路和方法，通过使用用于频率检测的附加回路来提高效率和抖动容限。 这种改进的电路包括用于识别初始恢复的时钟信号是否比接收的数据流的实际比特率更快或更慢的频率检测器。 频率检测器提供+/- 0.5 UI的抖动容限，并且使用其他常规频率检测器的显着较少的组件。 组件数量较少，功耗明显降低。 在一个实施例中，FD仅使用四个触发器，两个与门和一个延迟电路。 在集成电路中使用更少的组件也减少了管芯空间。 具有高抖动容限和更少的组件是比传统的无参考CDR电路的改进。