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公开(公告)号：US20240348420A1
公开(公告)日：2024-10-17
申请号：US18647834
申请日：2024-04-26
发明人： Jerzy A. Teterwak
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/087 , H04L7/0004
摘要： A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.
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公开(公告)号：US12120210B2
公开(公告)日：2024-10-15
申请号：US17993776
申请日：2022-11-23
申请人： Marvell Asia Pte Ltd
发明人： Basel Alnabulsi , Yu Liao , Benjamin Smith , Jamal Riani
CPC分类号： H04L7/0012 , H04L7/033
摘要： An input signal is sampled at a current sampling phase by a sampler device of a receiver device. The sampled input signal is equalized by an adaptive equalizer of the receiver device. One or more parameters of the adaptive equalizer are adapted, based on the equalized input signal, under one or more adaptation constraints. Phase gradient information indicative of an offset of the current sampling phase from an optimal sampling phase is determined, and the one or more adaptation constraints of the adaptive equalizer are updated based on the phase gradient information to move the current sampling phase towards the optimal sampling phase.
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公开(公告)号：US20240322994A1
公开(公告)日：2024-09-26
申请号：US18481226
申请日：2023-10-04
发明人： Michael Chung WANG , Neal HAYS , Amir AMIRKHANY
CPC分类号： H04L7/033 , H03L7/0807 , H03L7/099
摘要： A system and method of clock and data recovery. In some embodiments, the method includes: setting a bias signal source to a first bias value, the bias signal source being connected to an input of a voltage-controlled oscillator of a clock and data recovery circuit; determining that a locked signal of a frequency feedback signal source equals a first feedback value; setting the bias signal source to a second bias value, different from the first bias value; determining that a locked signal of the frequency feedback signal source equals a second feedback value; determining that the second feedback value meets a termination criterion; and setting an operating value of the bias signal source to the second bias value.
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公开(公告)号：US20240322829A1
公开(公告)日：2024-09-26
申请号：US18732176
申请日：2024-06-03
申请人： Ciena Corporation
CPC分类号： H03L7/0814 , H03L7/0994 , H03L7/1976 , H04L7/0037 , H04L7/033
摘要： A transceiver includes a first transmit (Tx) component configured to connect to a second receive (Rx) component in a second transceiver; a first Rx component configured to connect to a second Tx component in the second transceiver; a single Phase-Locked Loop (PLL) circuit connected to both the first Tx component and the first Rx component; and a control circuit configured to continuously calibrate a first Look-Up Table (LUT) configured to feed operating codes to a first phase rotator connected to an output of the single PLL circuit and to one of the first Tx component and the first Rx component. In an embodiment, the control circuit is further configured to continuously calibrate a second LUT configured to feed operating codes to a second phase rotator connected to an output of a single PLL circuit in the second transceiver.
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公开(公告)号：US12101094B2
公开(公告)日：2024-09-24
申请号：US18095472
申请日：2023-01-10
发明人： Daniel Hyman , Jeffrey Norris , Michael Dekoker , Anthony Aquino
CPC分类号： H03L7/099 , H03C3/0908 , H03F3/45475 , H04B1/0007 , H04B1/7136 , H04L7/033
摘要： An apparatus is comprised of a processor, a fast-locking Phase-Locked Loop Waveform Generator (PLLWG), an amplifier circuit, and a voltage controlled oscillator (VCO). The processor generates data program signals to program the PLLWG and generates a trigger command signal instructing the PLLWG to generate an analog tuning signal. The PLLWG, coupled to the processor, generates the analog tuning signal based on the trigger command signal. The amplifier circuit, coupled to the PLLWG, receives the analog tuning signal, amplify the analog tuning signal, and generates a control voltage. The VCO, coupled to the amplifier circuit, receives the control voltage and amplifies the control voltage to generate an amplified Radio Frequency (RF) channel frequency signal.
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公开(公告)号：US12066958B2
公开(公告)日：2024-08-20
申请号：US18135095
申请日：2023-04-14
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
CPC分类号： G06F13/1689 , G06F1/04 , G06F1/06 , G06F1/08 , G06F1/10 , G06F13/161 , G06F13/1657 , G11C7/222 , G11C7/04 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
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公开(公告)号：US20240275573A1
公开(公告)日：2024-08-15
申请号：US18644860
申请日：2024-04-24
申请人： SK hynix Inc.
发明人： Dae Sik PARK , Byung Cheol KANG , Seung Duk CHO
CPC分类号： H04L7/005 , H04L7/0079 , H04L7/0091 , H04L7/033
摘要： A method of operating an interface device including a first elastic buffer is provided. The method of operating the interface device includes performing a link equalization operation, checking a transmission mode of the interface device, and determining a transmission parameter of the interface device based on a status of the first elastic buffer or a status of a second elastic buffer included in another interface device communicating with the interface device when the transmission mode is a transmission parameter adjustment mode.
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公开(公告)号：US12034829B2
公开(公告)日：2024-07-09
申请号：US18155809
申请日：2023-01-18
发明人： Kenji Nakagawa , Koji Tomitsuka
摘要： A transmission device included in one base station in a radio communication system including communication areas adjacent to each other in which the base station communicates with a plurality of wireless terminals includes: a modulation unit that generates a data symbol sequence; a synchronization signal generating unit that generates a first symbol sequence constituted by two or more continuous repetitions of reference sequence symbols being a reference, generates a second symbol sequence by performing frequency shifting on the first symbol sequence by using a phase rotation sequence so that the reference sequence symbols become orthogonal for each of the wireless terminals, and generates a synchronization signal; and a synchronization signal adding unit that generates a transmission signal by adding the synchronization signal to the data symbol sequence.
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公开(公告)号：US12028192B2
公开(公告)日：2024-07-02
申请号：US18111862
申请日：2023-02-20
CPC分类号： H04L25/03057 , H04L7/0079 , H04L7/033
摘要： An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.
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公开(公告)号：US12021962B2
公开(公告)日：2024-06-25
申请号：US17203463
申请日：2021-03-16
发明人： Jing Yang Chen , Robert S. Nemiroff
IPC分类号： H04L7/033 , H04L43/106
CPC分类号： H04L7/033 , H04L43/106
摘要： A system and method are provided for encoding and decoding multiplexed video signals to de-jitter the content. A first de-jitter operation is performed on incoming signals and a second de-jitter operation is performed on PCR modified outbound packetized signals after sequencing of the packetized signals has been determined. In one case the second de-jitter operation can be performed using a PLL that is based, at least in part, on the output hardware limitations.
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