公开(公告)号：US20220392966A1

公开(公告)日：2022-12-08

申请号：US17568504

申请日：2022-01-04

Applicant: Samsung Display Co., Ltd.

Inventor： Kwang Soo LEE ,  Seul Ki KIM ,  Seung Rae KIM ,  Jae Hyun LEE ,  Seung Ha CHOI

IPC: H01L27/32

Abstract: Provided is a display device which comprises a substrate, a first insulating layer disposed on the substrate, a semiconductor layer disposed on the first insulating layer, wherein the semiconductor layer includes an active pattern, a second insulating layer disposed on the semiconductor layer, and a first conductive layer disposed on the second insulating layer. The display device further comprises a gate electrode and source/drain electrodes composed of the same conductive layer, and comprises a semiconductor layer having reduced resistance against an electrical signal applied to the transistor. Thus, reliability of the display device is improved due to the decrease in the resistance of the semiconductor layer.

公开(公告)号：US20190157459A1

公开(公告)日：2019-05-23

申请号：US16235779

申请日：2018-12-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang Soo LEE ,  Shin Hyuk YANG ,  Doo Hyun KIM ,  Jee Hoon KIM

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

公开(公告)号：US20180102383A1

公开(公告)日：2018-04-12

申请号：US15601338

申请日：2017-05-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jee Hoon KIM ,  Shin Hyuk YANG ,  Yong Hoon WON ,  Kwang Soo LEE

IPC: H01L27/12 ,  H01L27/32

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

公开(公告)号：US20170317216A1

公开(公告)日：2017-11-02

申请号：US15412278

申请日：2017-01-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Kwang Soo LEE ,  Shin Hyuk YANG ,  Doo Hyun KIM ,  Jee Hoon KIM

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L27/32

CPC classification number: H01L29/78606 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2227/323

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.