公开(公告)号：US20240347550A1

公开(公告)日：2024-10-17

申请号：US18755700

申请日：2024-06-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yang LV ,  Feng GUAN ,  Jianhua DU ,  Meng ZHAO ,  Hao WU ,  Chaolu WANG

IPC: H01L27/12

CPC classification number: H01L27/1251 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/127

Abstract: A method for preparing a driving backplane includes: providing a base substrate, forming a connecting layer on a side of the base substrate; forming an insulating layer group on a side of the connecting layer away from the base substrate, forming a first via hole by patterning the insulating layer group; forming inducing particles on a side of the insulating layer group away from the base substrate; forming a doped amorphous silicon layer on a side of the inducing particles away from the base substrate, forming a first conductor part by the doped amorphous silicon layer formed in the first via hole, forming a raw material part by patterning the doped amorphous silicon layer; and forming a first channel part by causing the inducing particles to induce the raw material part, wherein the first channel part is connected to the first conductor part.

公开(公告)号：US20240347542A1

公开(公告)日：2024-10-17

申请号：US18596237

申请日：2024-03-05

Applicant: Samsung Display Co., LTD.

Inventor： SEUL-KI KIM ,  JUNG KYOUNG CHO ,  JEONGJU PARK ,  ILBAE AHN

IPC: H01L27/12 ,  H10K59/12 ,  H10K59/121 ,  H10K59/123 ,  H10K59/131

CPC classification number: H01L27/1225 ,  H01L27/127 ,  H10K59/1201 ,  H10K59/1213 ,  H10K59/123 ,  H10K59/131

Abstract: A display panel includes a base substrate, a first transistor disposed on the base substrate and including a first semiconductor pattern layer and a first gate electrode, and a light emitting element disposed on the first transistor and electrically connected to the first transistor. The first semiconductor pattern layer may include a first active pattern layer disposed on the base substrate, a first drain contacting the first active pattern layer, and a first source contacting the first active pattern layer and spaced apart from the first drain. A first spaced region between the first drain and the first source may be defined as a first channel region of the first active pattern layer, and the first gate electrode may overlap the first channel region.

公开(公告)号：US12100711B2

公开(公告)日：2024-09-24

申请号：US17536648

申请日：2021-11-29

Applicant: SHARP KABUSHIKI KAISHA

Inventor： Masahiko Suzuki ,  Tetsuo Kikuchi ,  Setsuji Nishimiya ,  Kengo Hara ,  Hitoshi Takahata ,  Tohru Daitoh

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/124 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78696

Abstract: An active matrix substrate includes a plurality of oxide semiconductor TFTs, and a plurality of wiring line connection sections, each of the plurality of wiring line connection sections includes a first connection electrode, an interlayer insulating layer extending over the first connection electrode, a wiring line contact hole formed in an insulating layer including the interlayer insulating layer, the wiring line contact hole exposing a part of a metal oxide layer of a first connection electrode, and a second connection electrode, and the second connection electrode is connected to a part of the metal oxide layer of the first connection electrode in the wiring line contact hole.

公开(公告)号：US12100703B2

公开(公告)日：2024-09-24

申请号：US17897302

申请日：2022-08-29

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Yong Qiao ,  Xinyin Wu

IPC: H01L27/02 ,  H01L27/12 ,  H02H9/04

CPC classification number: H01L27/0292 ,  H01L27/027 ,  H01L27/1251 ,  H01L27/1259 ,  H01L27/127 ,  H01L27/0266 ,  H01L27/1222 ,  H01L27/124 ,  H02H9/045

Abstract: Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.

公开(公告)号：US12040410B2

公开(公告)日：2024-07-16

申请号：US18447360

申请日：2023-08-10

Applicant: Mikuni Electron Corporation

Inventor： Sakae Tanaka

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/66 ,  H10K59/12 ,  H10K59/121 ,  H10K59/124

CPC classification number: H01L29/78693 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78696 ,  H01L27/1248 ,  H10K59/1201 ,  H10K59/1213 ,  H10K59/124

Abstract: A transistor in an embodiment includes an oxide semiconductor layer on a substrate, the oxide semiconductor layer including a first region and a second region, a first gate electrode including a region overlapping the oxide semiconductor layer, the first gate electrode being arranged on a surface of the oxide semiconductor layer opposite to the substrate, a first insulating layer between the first gate electrode and the oxide semiconductor layer, and a first oxide conductive layer and a second oxide conductive layer between the oxide semiconductor layer and the substrate, the first oxide conductive layer and the second oxide conductive layer each including a region in contact with the oxide semiconductor layer.

公开(公告)号：US20240234440A1

公开(公告)日：2024-07-11

申请号：US18558740

申请日：2022-07-01

Applicant: Fuzhou BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Bin LIN ,  Yang WANG ,  Liangliang LI ,  Zengrong LI ,  Hangle GUO ,  Wenxing XI

IPC: H01L27/12

CPC classification number: H01L27/124 ,  H01L27/127

Abstract: Disclosed is a preparation method for an array substrate including: forming a first conductive portion on a substrate; sequentially forming a first insulating layer, a second insulating layer and a third insulating layer on the side of the first conductive portion that faces away from the substrate; forming, through one-time patterning process, a first sub-via that penetrates through the third insulating layer, the second insulating layer and a first part of the first insulating layer; forming a fourth insulating layer on the side of the third insulating layer that faces away from the substrate; etching and removing the fourth insulating layer and the first insulating layer of the second thickness that are at the first sub-via, so as to form a first via; and forming a first connection electrode on the side of the fourth insulating layer that faces away from the substrate.

公开(公告)号：US20240234434A1

公开(公告)日：2024-07-11

申请号：US17778415

申请日：2021-06-21

Applicant: Hefei Xinsheng Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Jie LEI ,  Zouming XU ,  Jian TIAN ,  Chunjian LIU ,  Xintao WU ,  Jie WANG ,  Jianying ZHANG

IPC: H01L27/12 ,  H01L25/075 ,  H01L25/18

CPC classification number: H01L27/124 ,  H01L25/0753 ,  H01L25/18 ,  H01L27/127

Abstract: Disclosed are a drive backplane, a preparation method therefor, and a display apparatus. The drive backplane includes a substrate, wherein the substrate includes a light emitting region and a bonding region, the light emitting region includes light emitting units arranged in an array, each light emitting unit includes a first signal line and a pad electrically connected with the first signal line; a first conductive layer, which is disposed on one side of the substrate and includes a first signal line and at least one signal detection line; and a second conductive layer, which is disposed on one side of the first conductive layer facing away from the substrate and includes: a pad; wherein the signal detection line is electrically connected with the pad of the light emitting unit.

公开(公告)号：US20240212774A1

公开(公告)日：2024-06-27

申请号：US18596906

申请日：2024-03-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Seiko AMANO ,  Kouhei TOYOTAKA ,  Hiroyuki MIYAKE ,  Aya MIYAZAKI ,  Hideaki SHISHIDO ,  Koji KUSUNOKI

IPC: G11C19/28 ,  G09G3/36 ,  G11C19/18 ,  H01L25/03 ,  H01L27/12 ,  H03K19/00 ,  H05K7/02

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G09G3/3696 ,  G11C19/184 ,  H01L25/03 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/1288 ,  H03K19/0013 ,  H05K7/02 ,  G09G2300/0809 ,  G09G2310/0286 ,  H01L2924/0002

Abstract: An object is to provide a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit. A pulse signal output circuit according to one embodiment of the disclosed invention includes first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit capable of operating stably and a shift register including the pulse signal output circuit can be provided.

公开(公告)号：US20240186327A1

公开(公告)日：2024-06-06

申请号：US18074814

申请日：2022-12-05

Applicant: Intel Corporation

Inventor： Hwichan Jun ,  Guillaume Bouche

IPC: H01L27/12 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/1237 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/127

Abstract: Techniques are provided herein to form semiconductor devices having different gate oxide thicknesses. A first semiconductor device includes a first gate structure around a first plurality of semiconductor nanoribbons and a second semiconductor device includes a second gate structure around a second plurality of semiconductor nanoribbons. The first gate structure includes at least a first gate oxide layer and a first gate electrode, and the second gate structure includes at least a second gate oxide layer and a second gate electrode. The first gate oxide layer is thicker than the second gate oxide layer. A high-k dielectric layer may be formed over the first and second gate oxide layers or may be formed over the second gate oxide layer, but not over the first gate oxide layer.

公开(公告)号：US20240178238A1

公开(公告)日：2024-05-30

申请号：US17789505

申请日：2021-06-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Dongfang WANG ,  Ce NING ,  Guangcai YUAN

IPC: H01L27/12

CPC classification number: H01L27/1244 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/127

Abstract: An array substrate includes: a base; gate lines and data lines on the base; multiple pixel units each including a thin film transistor; first and second conductive layers with a first insulating layer therebetween. The first conductive layer includes a first wiring pattern, the second conductive layer includes a first interconnection pattern, orthographic projections of the first wiring pattern and the first interconnection pattern on the base are at least partially overlapped. The first wiring pattern is connected with the first interconnection pattern through a via hole. Each of part of data lines is located in the first conductive layer and has an auxiliary line formed by the first interconnection pattern in the second conductive layer. The first wiring pattern includes the data lines; at least one of the data line and the first interconnection pattern is connected to a source of the thin film transistor.