公开(公告)号：US09536647B2

公开(公告)日：2017-01-03

申请号：US13715899

申请日：2012-12-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jin Woo Hahn ,  So Yeon Song ,  Sung Yong An ,  Byeong Cheol Moon ,  Soo Hwan Son

IPC: H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01F27/29

CPC classification number: H01F5/003 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/292

Abstract: There is provided a multi-layered chip electronic component including: a multi-layered body formed by stacking a plurality of magnetic layers; and conductive patterns disposed between the plurality of magnetic layers and electrically connected in a lamination direction to form coil patterns, wherein in a case in which a single coil pattern in the coil pattern is projected in the length and width directions of the multi-layered body, when an area of the magnetic layer inside of the coil pattern is defined as Ai and an area of the magnetic layer outside of the coil pattern is defined as Ao, 0.40≦Ai:Ao≦1.03 is satisfied.

Abstract translation: 提供了一种多层芯片电子部件，包括：通过堆叠多个磁性层而形成的多层体; 以及设置在所述多个磁性层之间并且在层叠方向上电连接以形成线圈图案的导电图案，其中在所述线圈图案中的单个线圈图案在所述多层体的长度和宽度方向上突出的情况下 当线圈图案内部的磁性层的面积被定义为Ai，并且将线圈图案外部的磁性层的面积定义为Ao时，则满足0.40≤Ai：Ao≤1.03。