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49 条记录 (耗时 0.018 秒)

    Multi-layered chip electronic component
    1.
    发明授权
    Multi-layered chip electronic component 有权
    多层芯片电子元器件

    公开(公告)号：US09536647B2

    公开(公告)日：2017-01-03

    申请号：US13715899

    申请日：2012-12-14

    申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

    发明人： Jin Woo Hahn ,  So Yeon Song ,  Sung Yong An ,  Byeong Cheol Moon ,  Soo Hwan Son

    IPC分类号： H01F5/00 ,  H01F27/28 ,  H01F17/00 ,  H01F27/29

    CPC分类号： H01F5/003 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/292

    摘要： There is provided a multi-layered chip electronic component including: a multi-layered body formed by stacking a plurality of magnetic layers; and conductive patterns disposed between the plurality of magnetic layers and electrically connected in a lamination direction to form coil patterns, wherein in a case in which a single coil pattern in the coil pattern is projected in the length and width directions of the multi-layered body, when an area of the magnetic layer inside of the coil pattern is defined as Ai and an area of the magnetic layer outside of the coil pattern is defined as Ao, 0.40≦Ai:Ao≦1.03 is satisfied.

    摘要翻译： 提供了一种多层芯片电子部件，包括：通过堆叠多个磁性层而形成的多层体; 以及设置在所述多个磁性层之间并且在层叠方向上电连接以形成线圈图案的导电图案，其中在所述线圈图案中的单个线圈图案在所述多层体的长度和宽度方向上突出的情况下 当线圈图案内部的磁性层的面积被定义为Ai，并且将线圈图案外部的磁性层的面积定义为Ao时，则满足0.40≤Ai：Ao≤1.03。

    Chip antenna module array
    8.
    发明授权
    Chip antenna module array 有权

    公开(公告)号：US11646504B2

    公开(公告)日：2023-05-09

    申请号：US17715425

    申请日：2022-04-07

    申请人： SAMSUNG ELECTRO-MECHANICS CO., LTD.

    发明人： Ju Hyoung Park ,  Young Sik Hur ,  Sung Yong An ,  Myeong Woo Han ,  Kyu Bum Han ,  Dae Ki Lim

    IPC分类号： H01Q1/22 ,  H01Q21/06

    CPC分类号： H01Q21/065 ,  H01Q1/2283

    摘要： A chip antenna module array includes a first chip antenna module including: a first solder layer disposed below a first dielectric layer; a first feed via disposed in the first dielectric layer; a first patch antenna pattern disposed above the first dielectric layer and having a first resonant frequency; and a first coupling pattern spaced apart from the first patch antenna pattern, and not vertically overlapping the first patch antenna pattern. The chip antenna module array includes a second chip antenna module including: a second solder layer disposed below a second dielectric layer; a second feed via disposed in the second dielectric layer; a second patch antenna pattern disposed above the second dielectric layer and having a second resonant frequency; and a second coupling pattern disposed above and vertically overlapping the second patch antenna pattern. The first and second chip antenna modules are disposed spaced apart on a connection member.

    Chip antenna
    9.
    发明授权
    Chip antenna 有权

    公开(公告)号：US11621491B2

    公开(公告)日：2023-04-04

    申请号：US17405286

    申请日：2021-09-01

    申请人： Samsung Electro-Mechanics Co., Ltd.

    发明人： Jae Yeong Kim ,  Chin Mo Kim ,  Ji Hyung Jung ,  Sung Nam Cho ,  Sung Yong An

    IPC分类号： H01Q1/22 ,  H01Q9/04 ,  H01Q1/48 ,  H01Q1/38

    摘要： A chip antenna includes a first substrate, a second substrate overlapping the first substrate, a first patch, provided on a first surface of the first substrate, operating as a feed patch, a second patch, provided on the second substrate, operating as a radiation patch, at least one feed via penetrating through the first substrate in a thickness direction and configured to provide a feed signal to the first patch, and a ground pad provided on the other surface of the first substrate. The first substrate comprises a ceramic sintered material. The ceramic sintered material comprises an Mg2SiO4 phase, an MgAl2O4 phase, and a CaTiO3 phase, and a content of the CaTiO3 phase in the ceramic sintered material ranges from 5.1 mol % to 15.1 mol %.