公开(公告)号：US20220059417A1

公开(公告)日：2022-02-24

申请号：US17520854

申请日：2021-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myeong-soon PARK ,  Hyun-Soo Chung ,  Chan-Ho Lee

IPC: H01L21/66 ,  G11C29/12

Abstract: A semiconductor chip is disclosed that includes a chip pad disposed in a first region of a chip body, a redistribution wiring test pad disposed in the first region of the chip body spaced apart from the chip pad and connected to the chip pad through a redistribution wiring structure, and a redistribution wiring connection pad disposed in the first region of the chip body or a second region of the chip body and connected to the chip pad through the redistribution wiring structure.

公开(公告)号：US20200013740A1

公开(公告)日：2020-01-09

申请号：US16283906

申请日：2019-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN-KUK BAE ,  Hyun-Soo Chung ,  Han-Sung Ryu ,  In-Young Lee ,  Chan-Ho Lee

IPC: H01L23/00

Abstract: A semiconductor chip includes a substrate. An electrode pad is disposed on the substrate. The electrode pad includes a low-k material layer. A first protection layer at least partially surrounds the electrode pad. The first protection layer includes a first opening at an upper portion thereof. A buffer pad is electrically connected to the electrode pad. A second protection layer at least partially surrounds the buffer pad. The second protection layer includes a second opening at an upper portion thereof. A pillar layer and a solder layer are sequentially stacked on the buffer pad. A thickness of the buffer pad is greater than a thickness of the electrode pad. A width of the first opening in a first direction parallel to an upper surface of the semiconductor substrate is equal to or greater than a width of the second opening in the first direction.

公开(公告)号：US09659137B2

公开(公告)日：2017-05-23

申请号：US14591439

申请日：2015-01-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Ho Lee

IPC: G06F17/50 ,  G06F11/22 ,  G06F13/12 ,  G06F11/10 ,  G06F11/27 ,  G06F12/06

CPC classification number: G06F17/5081 ,  G06F11/1068 ,  G06F11/2205 ,  G06F11/27 ,  G06F12/06 ,  G06F13/124 ,  G06F17/5068

Abstract: A method of verifying a layout of a mask read only memory (ROM) includes: receiving source ROM code, bitmap data, and layout design data of the mask ROM; generating coordinate data of a bit determining unit based on the layout design data; and determining an error cell based on the coordinate data of the bit determining unit, the bitmap data, and the source ROM code.