公开(公告)号：US20240362173A1

公开(公告)日：2024-10-31

申请号：US18475829

申请日：2023-09-27

申请人： Hamilton Sundstrand Corporation

发明人： Rajesh Madathikandam ,  Robin David Hill ,  Stephen Potter ,  Ashish Vijay ,  Rajeeva Krishna ,  Anitha Thangavel

IPC分类号： G06F13/12 ,  G06F11/10 ,  G06F13/16

CPC分类号： G06F13/124 ,  G06F11/1004 ,  G06F13/1668

摘要： A microprocessor-PLD hybrid architecture includes an IPC microprocessor and a PLD in signal communication with the IPC microprocessor via an IPC interface. The IPC microprocessor outputs a data read command to initiate a data read operation or a data write command. The PLD includes a plurality of PLD modules that store data and a bus controller. The bus controller communicates with the plurality of PLD modules via a plurality of PLD interfaces and is configured to sequentially execute a set of bus controller instructions. The bus controller reads data from a target PLD module from among the plurality of PLD modules in response to receiving the data read command, and transfers the data to the IPC microprocessor. The bus controller receives data from the IPC microprocessor and stores the data in a target PLD module from among the plurality of PLD modules in response to receiving the data write command.

公开(公告)号：US20240345981A1

公开(公告)日：2024-10-17

申请号：US18624296

申请日：2024-04-02

申请人： Other World Computing

发明人： Tal E. Volk ,  Farshid Tabrizi

IPC分类号： G06F13/40 ,  G06F13/12

CPC分类号： G06F13/4081 ,  G06F13/124 ,  G06F2213/3854

摘要： A dual connection peripheral device has a housing. A captive input/output cable is disposed at least partially within the housing and selectively connects the dual connection peripheral device to a host device. An auxiliary input/output port is disposed on the housing and selectively connects to the host. A control circuit is operatively coupled to the captive input/output cable and auxiliary input/output port and selectively connects one of the captive input/output cable and the auxiliary input/output port to the host device.

公开(公告)号：US20240184446A1

公开(公告)日：2024-06-06

申请号：US18441279

申请日：2024-02-14

申请人： Texas Instruments Incorporated

发明人： Kai CHIRCA ,  Daniel WU ,  Matthew David PIERSON

IPC分类号： G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0846 ,  G06F12/0855 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/12 ,  G06F13/16 ,  G06F13/40 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27

CPC分类号： G06F3/0604 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

摘要： Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

公开(公告)号：US11907528B2

公开(公告)日：2024-02-20

申请号：US17380297

申请日：2021-07-20

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Kai Chirca ,  Daniel Wu ,  Matthew David Pierson

IPC分类号： G06F3/06 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0855 ,  G06F13/16 ,  G06F12/0875 ,  G06F12/084 ,  G06F13/40 ,  G06F12/06 ,  G06F9/30 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F12/1009 ,  G06F12/10 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC分类号： G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

摘要： Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.

公开(公告)号：US11797473B2

公开(公告)日：2023-10-24

申请号：US16154517

申请日：2018-10-08

申请人： ALTERA CORPORATION

发明人： David Shippy ,  Martin Langhammer ,  Jeffrey Eastlack

IPC分类号： G06F15/78 ,  G06F9/30 ,  G06F9/38 ,  G06F13/28 ,  G06F9/54 ,  G06F17/14 ,  G06F13/12

CPC分类号： G06F15/7825 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/541 ,  G06F13/124 ,  G06F13/28 ,  G06F17/142

摘要： An accelerated processor structure on a programmable integrated circuit device includes a processor and a plurality of configurable digital signal processors (DSPs). Each configurable DSP includes a circuit block, which in turn includes a plurality of multipliers. The accelerated processor structure further includes a first bus to transfer data from the processor to the configurable DSPs, and a second bus to transfer data from the configurable DSPs to the processor.

公开(公告)号：US11687238B2

公开(公告)日：2023-06-27

申请号：US17408552

申请日：2021-08-23

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Matthew David Pierson ,  Daniel Wu ,  Kai Chirca

IPC分类号： G06F3/06 ,  G06F12/084 ,  G06F13/16 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/0875 ,  G06F12/10 ,  G06F13/40 ,  G06F12/0855 ,  G06F12/06 ,  G06F12/0817 ,  G06F12/0831 ,  G06F13/12 ,  G06F12/0815 ,  H03M13/01 ,  H03M13/09 ,  H03M13/15 ,  H03M13/27 ,  G06F9/30 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/0862

CPC分类号： G06F3/0604 ,  G06F3/064 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/3897 ,  G06F9/4881 ,  G06F9/5016 ,  G06F12/0607 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0857 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1663 ,  G06F13/1668 ,  G06F13/4027 ,  H03M13/015 ,  H03M13/098 ,  H03M13/1575 ,  H03M13/276 ,  H03M13/2785 ,  G06F12/0833 ,  G06F12/0846 ,  G06F12/0851 ,  G06F12/0862 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/1048 ,  G06F2212/304 ,  G06F2212/452 ,  G06F2212/6024 ,  G06F2212/657

摘要： A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

公开(公告)号：US20190004987A1

公开(公告)日：2019-01-03

申请号：US15639832

申请日：2017-06-30

申请人： Western Digital Technologies, Inc.

发明人： James V. Henson

IPC分类号： G06F13/38 ,  G06F13/42 ,  G06F13/12 ,  G06F13/40 ,  G06F13/24 ,  G06F15/78

CPC分类号： G06F13/387 ,  G06F13/124 ,  G06F13/24 ,  G06F13/4022 ,  G06F13/404 ,  G06F13/4282 ,  G06F15/7825

摘要： A method and system for adapting communication between a low-speed interface and a high-speed interface is disclosed. The method includes retrieving configuration instructions in response to a power-up of a microcontroller, where the configuration instructions associated with a low-speed communication protocol. The method includes sending the configuration instructions to a low-speed interface module causing the low-speed interface module to configure an interface of the low-speed interface module based on the configuration instructions. The method includes receiving, by the interface of the low-speed interface module, data associated with the low-speed communication protocol. The method includes retrieving, by the microcontroller, mapping instructions associated with a high-speed communication protocol. The method also includes sending, by the microcontroller, the mapping instructions to the low-speed interface module, causing the low-speed interface module to convert the data associated with the low-speed communication protocol to data associated with the high-speed communication protocol.

公开(公告)号：US20180300275A1

公开(公告)日：2018-10-18

申请号：US15821492

申请日：2017-11-22

申请人： Intel Corporation

发明人： Zuoguo J. Wu ,  Mahesh Wagh ,  Debendra Das Sharma ,  Gerald S. Pasdast ,  Ananthan Ayyasamy ,  Xiaobei Li ,  Robert G. Blankenship ,  Robert J. Safranek

IPC分类号： G06F13/40 ,  G06F1/10

CPC分类号： G06F13/4022 ,  G06F1/10 ,  G06F13/124 ,  G06F13/4273 ,  G06F13/4282 ,  G06F15/173 ,  Y02D10/14 ,  Y02D10/151

摘要： Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

公开(公告)号：US20180189198A1

公开(公告)日：2018-07-05

申请号：US15805879

申请日：2017-11-07

申请人： GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.

发明人： Jian BAI

IPC分类号： G06F13/12 ,  G06F13/42 ,  G06F1/28 ,  G06F1/26 ,  G06F13/40

CPC分类号： G06F13/124 ,  G06F1/266 ,  G06F1/28 ,  G06F13/4022 ,  G06F13/4031 ,  G06F13/4068 ,  G06F13/4282

摘要： The embodiments of the disclosure disclose a communication method between peripheral devices of a mobile terminal and a mobile terminal. The mobile terminal includes at least two peripheral device and a bus, wherein each of the at least two peripheral devices is directly connected to the bus, and the at least two peripheral devices communicate with each other via the bus. A first peripheral device of the at least two peripheral devices is configured to send, when the first peripheral device needs to access a second peripheral device of the at least two peripheral devices, an access instruction to the second peripheral device via the bus; and the second peripheral device is configured to receive the access instruction, and execute an operation corresponding to the access instruction.

公开(公告)号：US10007465B2

公开(公告)日：2018-06-26

申请号：US14826583

申请日：2015-08-14

申请人： MICRON TECHNOLOGY, INC.

发明人： Lance Dover ,  Jim Cooke ,  Peter Feeley

IPC分类号： G06F12/00 ,  G06F3/06 ,  G06F11/10 ,  G06F13/16 ,  G06F12/06 ,  G06F12/02 ,  G06F13/12

CPC分类号： G06F3/065 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/1076 ,  G06F12/0223 ,  G06F12/0246 ,  G06F12/0638 ,  G06F13/124 ,  G06F13/1642 ,  G06F13/1673 ,  G06F2212/7205 ,  G06F2212/7207

摘要： Methods of operating a memory device, and memory devices and systems so configured, include receiving a first address range for programming user data to a first range of physical memory addresses of a memory device, receiving a second address range for programming associated metadata to a second range of physical memory addresses of the memory device, determining whether the first address range is contiguous with the second address range, maintaining the second range of physical memory addresses for programming the metadata when it is determined that the second address range is contiguous with the first address range, and, when it is determined that the second address range is not contiguous with the first address range, remapping the second address range to a third range of physical memory addresses of the memory contiguous with the first range of physical memory addresses for programming the metadata.