公开(公告)号：US20200051976A1

公开(公告)日：2020-02-13

申请号：US16290199

申请日：2019-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Seok HA ,  Hyun Seung SONG ,  Hyo Jin KIM ,  Kyoung Mi PARK ,  Guk Il AN

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

公开(公告)号：US20180358358A1

公开(公告)日：2018-12-13

申请号：US15801797

申请日：2017-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Kwan YU ,  Won Hyung KANG ,  Hyo Jin KIM ,  Sung Bu MIN

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7853

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.

公开(公告)号：US20220231168A1

公开(公告)日：2022-07-21

申请号：US17657761

申请日：2022-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo Jin KIM ,  Dong Woo KIM ,  Sang Moon LEE ,  Seung Hun LEE

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/786 ,  H01L27/092

Abstract: A semiconductor device includes first and second fin-shaped patterns disposed on a substrate and extending in a first direction, first and second channel layers disposed on the first and second fin-shaped patterns, first and second etch stop layers disposed inside the first and second channel layers, first and second gate structures extending in a second direction different from the first direction on the first channel layer with a first recess formed therebetween, third and fourth gate structures extending in the second direction on the second channel layer with a second recess formed therebetween, the first recess having a first width in the first direction and having a first depth in a third direction perpendicular to the first and second directions, the second recess having a second width different from the first width in the first direction, and having a second depth equal to the first depth in the third direction.

公开(公告)号：US20180342583A1

公开(公告)日：2018-11-29

申请号：US15800483

申请日：2017-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Kwan YU ,  Hyo Jin KIM ,  Ryong HA

IPC: H01L29/08 ,  H01L27/092 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/76224 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/7848 ,  H01L29/7854

Abstract: A semiconductor device is provided. The semiconductor device includes a fin-type pattern formed on a substrate and including first and second sidewalls, which are defined by a trench, a field insulating film placed in contact with the first and second sidewalls and filling the trench, and an epitaxial pattern formed on the fin-type pattern and including a first epitaxial layer and a second epitaxial layer, which is formed on the first epitaxial layer.

公开(公告)号：US20170255735A1

公开(公告)日：2017-09-07

申请号：US15343860

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin KIM ,  Su Hyeon KIM ,  Azmat RAHEEL ,  Chul Hong PARK

IPC: G06F17/50 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: G06F17/5072 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.