公开(公告)号：US20180090492A1

公开(公告)日：2018-03-29

申请号：US15473913

申请日：2017-03-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rajeev RANJAN ,  Deepak SHARMA ,  Subhash KUCHANURI ,  Chul Hong PARK ,  Jae Seok YANG ,  Kwan Young CHUN

IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L23/522

Abstract: Integrated circuit devices are provided. The IC devices may include an active region extending in a first direction, first and second gate electrodes extending in a second direction, a first impurity region in the active region adjacent a first side of the first gate electrode, a second impurity region in the active region between a second side of the first gate electrode and a first side of the second gate electrode, a third impurity region in the active region adjacent a second side of the second gate electrode, a cross gate contact electrically connecting the first and second impurity regions, a first contact electrically connected to the third impurity region, a first wire electrically connected to the cross gate contact, and a second wire electrically connected to the first contact. The first and second wires may extend only in the first direction and may be on the same line.

公开(公告)号：US20190355719A1

公开(公告)日：2019-11-21

申请号：US16372166

申请日：2019-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shigenobu MAEDA ,  Sung Chul PARK ,  Chul Hong PARK ,  Yoshinao HARADA ,  Sung Min KANG ,  Ji Wook KWON ,  Ha-Young KIM ,  Yuichi HIRANO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/40

Abstract: A semiconductor device includes first to fourth cells sequentially disposed on a substrate, first to third diffusion break structures, a first fin structure configured to protrude from the substrate, the first fin structure comprising first to fourth fins separated from each other by the first to third diffusion break structures, a second fin structure configured to protrude from the substrate, to be spaced apart from the first fin structure, the second fin structure comprising fifth to eighth fins separated from each other by the first to third diffusion break structures, the first to fourth gate electrodes being disposed in the first to fourth cells, respectively, and the number of fins in one cell of the first to fourth cells is different from the number of fins in an other cell of the first to fourth cells.

公开(公告)号：US20190051600A1

公开(公告)日：2019-02-14

申请号：US15873352

申请日：2018-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Wook OH ,  Dong Hyun KIM ,  Doo Hwan PARK ,  Sung Keun PARK ,  Chul Hong PARK ,  Sung Wook HWANG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L21/311

Abstract: A semiconductor device includes a plurality of main contact plugs and a plurality of dummy contact plugs which pass through an insulating layer on a substrate. A plurality of upper interconnections is on the insulating layer. The plurality of dummy contact plugs include a first dummy contact plug. The plurality of upper interconnections include a first upper interconnection overlapping the first dummy contact plug. A vertical central axis of the first dummy contact plug is located outside the first upper interconnection.

公开(公告)号：US20170255735A1

公开(公告)日：2017-09-07

申请号：US15343860

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo Jin KIM ,  Su Hyeon KIM ,  Azmat RAHEEL ,  Chul Hong PARK

IPC: G06F17/50 ,  H01L29/423 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: G06F17/5072 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided. The fabricating method of a semiconductor device includes loading a first layout, wherein the first layout comprises a first active region and a first dummy region, and the first active region comprises a fin-type pattern design having a first width, generating a second layout by substituting the fin-type pattern design with a nanowire structure design and forming a nanowire structure by using the second layout, wherein the second layout comprises a second active region in the same size as the first active region, and a second dummy region in the same size as the first dummy region, the nanowire structure design has a second width greater than the first width, and the nanowire structure comprises a first nanowire extending in a first direction, a second nanowire extending in the first direction and being formed on the first nanowire at a spacing apart from the first nanowire, a gate electrode surrounding a periphery of the first nanowire and extending in a second direction of intersecting with the first direction, a gate spacer being formed on a sidewall of the gate electrode and comprising an inner sidewall and an outer sidewall facing each other, the inner sidewall of the gate spacer facing a side surface of the gate electrode, and a source/drain epitaxial layer on at least one side of the gate electrode and being connected to the first nanowire.