公开(公告)号：US11664316B2

公开(公告)日：2023-05-30

申请号：US16849085

申请日：2020-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseung Lee ,  Jinnam Kim ,  Hyoukyung Cho ,  Taeseong Kim ,  Kwangjin Moon

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/5385 ,  H01L2224/08146

Abstract: A semiconductor device may include a first semiconductor substrate having a first surface and a second surface opposite to each other, a first circuit layer provided on the first surface of the first semiconductor substrate, a connection pad provided on the second surface of the first semiconductor substrate, and a first penetration via and a second penetration via penetrating the first semiconductor substrate and at least a portion of the first circuit layer. The first penetration via and the second penetration via may be provided in a first penetration hole and a second penetration hole, respectively. Each of the first and second penetration holes may include a first portion, a second portion, and a third portion. A width of the first portion of the first penetration hole may be smaller than a width of the first portion of the second penetration hole.

公开(公告)号：US11315894B2

公开(公告)日：2022-04-26

申请号：US17035215

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyungjun Jeon ,  Kwangjin Moon ,  Hakseung Lee ,  Hyoukyung Cho

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/683 ,  H01L21/78 ,  H01L25/00

Abstract: A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.