公开(公告)号：US20240363489A1

公开(公告)日：2024-10-31

申请号：US18754081

申请日：2024-06-25

Applicant: Yibu Semiconductor Co., Ltd.

Inventor： Ming Li

IPC: H01L23/473 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L23/00 ,  H01L23/48 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L23/473 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/308 ,  H01L23/481 ,  H01L24/80 ,  H01L24/08 ,  H01L24/16 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/1431 ,  H01L2924/1436 ,  H10B80/00

Abstract: The present disclosure relates to a chip stack in the semiconductor field and a method of manufacturing the same. The chip stack comprises a plurality of stacked chips, the active surface of a first chip of the plurality of chips facing the passive surface of a second chip immediately below the first chip, and at least one open cavity embedded in the passive surface of the second chip forming a closed micro-channel with the active surface of the first chip. The microchannels in the stacked chips allow cooling micro-fluid to be introduced into the microchannels. The micro-fluid can flow from one chip to another, taking away heat generated by the chips, allowing heat dissipation of the chip stack to meet industry requirement. The micro-channels for dissipating the heat are formed while the chips are stacked. Thus, besides forming the micro-channels, no additional process steps are required to form the chip stack.

公开(公告)号：US20240304504A1

公开(公告)日：2024-09-12

申请号：US18598077

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Boin NOH ,  Yongho KIM ,  Sunoo KIM

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L22/32 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/08146 ,  H01L2224/08155 ,  H01L2224/16146 ,  H01L2224/16157 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

Abstract: A semiconductor package includes: a semiconductor chip including an active layer; a bump pad positioned on the active layer; a passivation layer covering the bump pad and including a first opening and a second opening, wherein the first opening exposes a first portion of the second surface of the bump pad, and the second opening exposes a second portion of the second surface of the bump pad; a first bump disposed on the first portion of the second surface of the bump pad, which is exposed through the first opening; and a test bump disposed on the second portion of the second surface of the bump pad, which is exposed through the second opening, wherein the first bump includes at least one metal layer, and a length of the test bump in a vertical direction is less than a length of the first bump in the vertical direction.

公开(公告)号：US12087732B2

公开(公告)日：2024-09-10

申请号：US18338013

申请日：2023-06-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Tsu Chung ,  Ku-Feng Yang ,  Yung-Chi Lin ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/683 ,  H01L21/82 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L21/6836 ,  H01L21/82 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06582

Abstract: A semiconductor package including an improved isolation bonding film and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first die bonded to a package substrate, the first die including vias extending through a substrate, the vias extending above a top surface of the substrate; a first dielectric film extending along a top surface of the package substrate, along the top surface of the substrate, and along sidewalls of the first die, the vias extending through the first dielectric film; a second die bonded to the first dielectric film and the vias; and an encapsulant over the package substrate, the first die, the first dielectric film, and the second die.

公开(公告)号：US20240258228A1

公开(公告)日：2024-08-01

申请号：US18541630

申请日：2023-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juneyoung Park ,  Heonjong Shin ,  Jaeran Jang ,  Doohyun Lee

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/08137 ,  H01L2224/08146 ,  H01L2224/16137 ,  H01L2224/16227 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01073 ,  H01L2924/1431 ,  H01L2924/1435 ,  H01L2924/19041

Abstract: An integrated circuit device includes a first substrate having a first surface and a second surface opposite to the first surface, and including an active device therein, BEOL structure disposed on the first surface of the first substrate and configured to route signals, a second substrate disposed on the first surface of the first substrate with the first BEOL structure disposed therebetween, and including a passive device therein, a power distribution structure disposed on the second surface of the first substrate, a first bonding structure positioned on the first BEOL structure, and a second bonding structure disposed between the first bonding structure and the second substrate.

公开(公告)号：US20240234252A1

公开(公告)日：2024-07-11

申请号：US18380325

申请日：2023-10-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： SHING-YIH SHIH

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L21/76831 ,  H01L21/76852 ,  H01L21/76898 ,  H01L23/53238 ,  H01L23/5329 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06541

Abstract: The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.

公开(公告)号：US20240222300A1

公开(公告)日：2024-07-04

申请号：US18610263

申请日：2024-03-20

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05557 ,  H01L2224/08146 ,  H01L2224/80143

Abstract: Semiconductor devices having interconnect structures with vertically offset bonding surfaces, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a semiconductor substrate at least partially covered by a first dielectric material having an upper surface, and an interconnect structure extending therefrom. The interconnect structure can include a plurality of conductive elements, and a continuous region of a first insulating material at least partially between the plurality of conductive elements. The plurality of conductive elements and the continuous region can have coplanar end surfaces. The interconnect structure can further include a perimeter structure at least partially surrounding the plurality of conductive elements and the continuous region. The perimeter structure can have an uppermost surface that can be vertically offset from the upper surface of the first dielectric material and/or the coplanar end surfaces.

公开(公告)号：US12021103B2

公开(公告)日：2024-06-25

申请号：US17870865

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Bo-Tsung Tsai

IPC: H01L27/146 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L25/00

CPC classification number: H01L27/14634 ,  H01L21/78 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/08 ,  H01L24/89 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14687 ,  H01L27/1469 ,  H01L23/53228 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80011 ,  H01L2224/8012 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20108 ,  H01L2924/20109 ,  H01L2924/2011

Abstract: A hybrid bonded structure including a first integrated circuit component and a second integrated circuit component is provided. The first integrated circuit component includes a first dielectric layer, first conductors and isolation structures. The first conductors and the isolation structures are embedded in the first dielectric layer. The isolation structures are electrically insulated from the first conductors and surround the first conductors. The second integrated circuit component includes a second dielectric layer and second conductors. The second conductors are embedded in the second dielectric layer. The first dielectric layer is bonded to the second dielectric layer and the first conductors are bonded to the second conductors.

公开(公告)号：US12021067B2

公开(公告)日：2024-06-25

申请号：US18389752

申请日：2023-12-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/473 ,  H01L23/48 ,  H10B80/00

CPC classification number: H01L25/0657 ,  H01L23/473 ,  H01L23/481 ,  H01L24/08 ,  H10B80/00 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2924/1421 ,  H01L2924/1431

Abstract: A 3D device, the device including: at least one first level including logic circuits; at least one second level bonded to the first level, where the at least one second level includes a plurality of transistors; connectivity structures, where the connectivity structures include a plurality of transmission lines, where the plurality of transmission lines are designed to conduct radio frequencies (“RF”) signals, and where the bonded includes oxide to oxide bond regions and metal to metal bond regions; and a plurality of vias disposed through the at least one second level, where at least a majority of the plurality of vias have a diameter of less than 5 micrometers.

公开(公告)号：US12015008B2

公开(公告)日：2024-06-18

申请号：US17869977

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chi Lin ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC: H01L25/065 ,  B23K26/362 ,  H01L21/3213 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  B23K26/362 ,  H01L21/32136 ,  H01L24/03 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/37001

Abstract: In an embodiment, a device includes: a first wafer including a first substrate and a first interconnect structure, a sidewall of the first interconnect structure forming an obtuse angle with a sidewall of the first substrate; and a second wafer bonded to the first wafer, the second wafer including a second substrate and a second interconnect structure, the sidewall of the first substrate being laterally offset from a sidewall of the second substrate and a sidewall of the second interconnect structure.

公开(公告)号：US20240178187A1

公开(公告)日：2024-05-30

申请号：US18430903

申请日：2024-02-02

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shanghsuan CHIANG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/16 ,  H01L2224/0801 ,  H01L2224/08146 ,  H01L2224/16014 ,  H01L2224/16146 ,  H01L2924/15311 ,  H01L2924/182 ,  H01L2924/3511

Abstract: A chip package structure includes: a substrate, a first connection chip, conductive columns, a first packaging layer, a first chip, and a second chip. The first connection chip is disposed on the substrate. The conductive columns is disposed on the substrate and located on a periphery of the first connection chip. The first packaging layer is disposed on the substrate and wrapping the first connection chip and the conductive columns, with the active surface of the first connection chip and top surfaces of the conductive columns exposed. The first chip is disposed on the first packaging layer, and coupled to both the conductive columns and the first connection chip. The second chip is disposed on the first packaging layer and that is away from the substrate, and coupled to both the conductive columns and the first connection chip.