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公开(公告)号:US20220077129A1
公开(公告)日:2022-03-10
申请号:US17204394
申请日:2021-03-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JUNGTAE SUNG , JUNYOUNG CHOI , JIYOUNG KIM , YOONJO HWANG
IPC: H01L25/18 , H01L25/065 , H01L23/00 , H01L27/11529 , H01L27/11556 , H01L27/11573 , H01L27/11582 , H01L25/00
Abstract: Disclosed are three-dimensional semiconductor memory devices and electronic systems including the same. The three-dimensional semiconductor memory device comprises a first structure and a second structure in contact with the first structure. Each of the first and second structures includes a substrate, a peripheral circuit region on the substrate, and a cell array region including a stack structure on the peripheral circuit region, a plurality of vertical structures that penetrate the stack structure, and a common source region in contact with the vertical structures. The stack structure is between the peripheral circuit region and the common source region. The common source regions of the first and second structures are connected with each other.
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公开(公告)号:US20210057419A1
公开(公告)日:2021-02-25
申请号:US16833919
申请日:2020-03-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: DONGSUK SHIN , JIYOUNG KIM , HOKYUN AN , CHAN MIN LEE , EUNJU CHO , HUI-JUNG KIM , JOONGCHAN SHIN , TAEHYUN AN , HYUNGEUN CHOI , YOOSANG HWANG , KISEOK LEE
IPC: H01L27/108
Abstract: A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.
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