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    SEMICONDUCTOR DEVICES INCLUDING SOURCE/DRAIN REGIONS HAVING MULTIPLE EPITAXIAL PATTERNS
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING SOURCE/DRAIN REGIONS HAVING MULTIPLE EPITAXIAL PATTERNS 有权
    半导体器件，包括具有多个外延模式的源/漏区

    公开(公告)号：US20150380553A1

    公开(公告)日：2015-12-31

    申请号：US14673519

    申请日：2015-03-30

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： KEUM SEOK PARK ,  JUNGHO YOO ,  JINYEONG JOE ,  BONYOUNG KOO ,  DONGSUK SHIN ,  HONGSIK YOON ,  BYEONGCHAN LEE

    IPC分类号： H01L29/78 ,  H01L29/165

    CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02636 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/785

    摘要： A semiconductor device includes an active pattern protruding from a substrate, a gate structure crossing over the active pattern, and source/drain regions disposed on the active pattern at opposite sides of the gate structure. Each of the source/drain regions includes a first epitaxial pattern contacting the active pattern and a second epitaxial pattern on the, first epitaxial pattern. The first epitaxial pattern comprises a material having a lattice constant which is the same as that of the substrate, and the second epitaxial pattern comprises a material having a lattice constant greater than that of the first epitaxial pattern.

    摘要翻译： 半导体器件包括从衬底突出的有源图案，在有源图案上交叉的栅极结构以及设置在栅极结构的相对侧上的有源图案上的源极/漏极区域。 源极/漏极区域中的每一个包括接触有源图案的第一外延图案和第一外延图案上的第二外延图案。 第一外延图案包括具有与衬底相同的晶格常数的材料，并且第二外延图案包括具有大于第一外延图案的晶格常数的晶格常数的材料。

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057419A1

    公开(公告)日：2021-02-25

    申请号：US16833919

    申请日：2020-03-30

    申请人： Samsung Electronics Co., Ltd.

    发明人： DONGSUK SHIN ,  JIYOUNG KIM ,  HOKYUN AN ,  CHAN MIN LEE ,  EUNJU CHO ,  HUI-JUNG KIM ,  JOONGCHAN SHIN ,  TAEHYUN AN ,  HYUNGEUN CHOI ,  YOOSANG HWANG ,  KISEOK LEE

    IPC分类号： H01L27/108

    摘要： A semiconductor memory device includes a substrate having a cell region and a contact region with a peripheral circuit region, first and second stacks on the cell region, and a first peripheral transistor on the peripheral circuit region. Each of the first and second stacks includes semiconductor patterns stacked, in a vertical direction, on the cell region, bit lines stacked in the vertical direction on the cell region and respectively connected to first ends of the semiconductor patterns, each of the bit lines extending, in a horizontal direction with respect to the upper surface of the substrate, from the cell region to the contact region, and a word line disposed adjacent to the semiconductor patterns and extending in the vertical direction from the cell region of the substrate. The first peripheral transistor is disposed between the bit lines of the first stack and the bit lines of the second stack.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    8.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220416082A1

    公开(公告)日：2022-12-29

    申请号：US17585686

    申请日：2022-01-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： SUJIN JUNG ,  JINBUM KIM ,  DAHYE KIM ,  INGYU JANG ,  DONGSUK SHIN

    IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/08

    摘要： Disclosed are a semiconductor device and a method of fabricating the same, the semiconductor device including an active pattern on a substrate, a source/drain pattern on the active pattern, a channel pattern on the active pattern, connected to the source/drain pattern, and including stacked semiconductor patterns, a gate electrode extending in a first direction and crossing the channel pattern, and a gate insulating layer between the gate electrode and the channel pattern. The source/drain pattern includes first and second semiconductor layers, the first semiconductor layer including a center portion including a second outer side surface in contact with the gate insulating layer and an edge portion adjacent to a side of the center portion and including a first outer side surface in contact with the gate insulating layer. The second outer side surface is further recessed toward the second semiconductor layer, compared with the first outer side surface.

    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150145072A1

    公开(公告)日：2015-05-28

    申请号：US14562937

    申请日：2014-12-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： DONG HYUK KIM ,  HOI SUNG CHUNG ,  MYUNGSUN KIM ,  DONGSUK SHIN

    IPC分类号： H01L29/78 ,  H01L29/06

    CPC分类号： H01L29/7834 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0692 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

    摘要： A MOS transistor includes a pair of impurity regions formed in a substrate as spaced apart from each other, and a gate electrode formed on a region of the substrate located between the pair of impurity regions. Each of the impurity regions is formed of a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer. The first epitaxial layer is formed of at least one first sub-epitaxial layer and a respective second sub-epitaxial layer stacked on each first sub-epitaxial layer. An impurity concentration of the first sub-epitaxial layer is less than that of the second sub-epitaxial layer.

    摘要翻译： MOS晶体管包括在彼此间隔开的基板中形成的一对杂质区，以及形成在位于该对杂质区之间的基板的区域上的栅电极。 每个杂质区由第一外延层，第一外延层上的第二外延层和第二外延层上的第三外延层形成。 第一外延层由堆叠在每个第一子外延层上的至少一个第一子外延层和相应的第二子外延层形成。 第一子外延层的杂质浓度小于第二子外延层的杂质浓度。