公开(公告)号：US10211196B2

公开(公告)日：2019-02-19

申请号：US15234532

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyok Ko ,  Min-Chang Ko ,  Han-Gu Kim ,  Jong-Kyu Song ,  Jin Heo

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/78 ,  H01L29/66

Abstract: An electrostatic discharge (ESD) protection device includes an N-type laterally diffused metal oxide semiconductor (LDMOS) transistor including a source electrode, a gate electrode, and a well bias electrode that are connected to a first pad receiving a first voltage, and a drain electrode connected to a middle node. The ESD protection device further includes a silicon controlled rectifier (SCR) connected between the middle node and a second pad receiving a second voltage higher than the first voltage.

公开(公告)号：US12254905B2

公开(公告)日：2025-03-18

申请号：US18103080

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonki Kim ,  Keunha Choi ,  Jin Heo

IPC: G11B27/10 ,  G11B27/34

Abstract: An electronic device includes: a display; and a processor configured to: play a video on the display by using a first application, obtain playback information associated with playing the video by using the first application, activate a second application while the video is played by using the first application, determine a frame of the video corresponding to a time point at which the second application is activated, and seek the frame to play the video by using the second application, based on the second application being able to seek the frame within a reference time.

公开(公告)号：US12238452B2

公开(公告)日：2025-02-25

申请号：US18103422

申请日：2023-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Heo ,  Jaehyeon Jeong

IPC: H04N7/01 ,  G09G5/00 ,  G09G5/14 ,  H04N5/783 ,  H04N13/139 ,  H04N13/332 ,  H04N21/4402 ,  H04N21/462 ,  H04N21/81

Abstract: Disclosed is an electronic device including a display module and a processor. The processor is configured to obtain a first video frame and a bypass control value for the first video frame and determine whether to perform frame rate conversion (FRC) processing using the first video frame based on the bypass control value. Based on a determination that the bypass control value is set to a first value indicating bypass of the FRC processing, the processor is configured to display the first video frame. Based on a determination that the bypass control value is set to a second value indicating the FRC processing, the processor is configured to generate an interpolation frame using the first video frame and a second video frame after the first video frame, and display the first video frame, the interpolation frame, and the second video frame.