公开(公告)号：US20250077182A1

公开(公告)日：2025-03-06

申请号：US18953922

申请日：2024-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinook SONG ,  Daekyeung KIM ,  Junseok PARK ,  Joonho SONG ,  Sehwan LEE ,  Junwoo JANG ,  Yunkyo CHO

IPC: G06F7/544 ,  G06N3/063

Abstract: An arithmetic apparatus includes a first operand holding circuit configured to output a first operand according to a clock signal, generate an indicator signal based on bit values of high-order bit data including a most significant bit of the first operand, and gate the clock signal based on the indicator signal, the clock signal being applied to a flip-flop latching the high-order bit data of the first operand; a second operand holding circuit configured to output a second operand according to the clock signal; and an arithmetic circuit configured to perform data gating on the high-order bit data of the first operand based on the indicator signal and output an operation result by performing an operation using a modified first operand resulting from the data gating and the second operand.

公开(公告)号：US20230252298A1

公开(公告)日：2023-08-10

申请号：US18304574

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho SONG ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/08 ,  G06F17/15 ,  G06N3/045 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06F17/153 ,  G06N3/045 ,  G06N3/04

Abstract: A neural network apparatus configured to perform a deconvolution operation includes a memory configured to store a first kernel; and a processor configured to: obtain, from the memory, the first kernel; calculate a second kernel by adjusting an arrangement of matrix elements comprised in the first kernel; generate sub-kernels by dividing the second kernel; perform a convolution operation between an input feature map and the sub-kernels using a convolution operator; and generate an output feature map, as a deconvolution of the input feature map, by merging results of the convolution operation.

公开(公告)号：US20220335284A1

公开(公告)日：2022-10-20

申请号：US17848007

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Namjoon KIM ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: A neural network apparatus includes a plurality of node buffers connected to a node lane and configured to store input node data by a predetermined bit size; a plurality of weight buffers connected to a weight lane and configured to store weights; and one or more processors configured to: generate first and second split data by splitting the input node data by the predetermined bit size, store the first and second split data in the node buffers, output the first split data to an operation circuit for a neural network operation on an index-by-index basis, shift the second split data, and output the second split data to the operation circuit on the index-by-index basis.

公开(公告)号：US20240362471A1

公开(公告)日：2024-10-31

申请号：US18764864

申请日：2024-07-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sehwan LEE ,  Namjoon KIM ,  Joonho SONG ,  Junwoo JANG

IPC: G06N3/063 ,  G06F17/15 ,  G06N3/04 ,  G06N3/045 ,  G06T1/20

CPC classification number: G06N3/063 ,  G06F17/15 ,  G06N3/04 ,  G06N3/045 ,  G06T1/20

Abstract: Provided are a method and apparatus for processing a convolution operation in a neural network, the method includes determining a precision of feature map operands and a precision of weight operands, respectively, on which the convolution operation is to be performed in parallel, decomposing a multiplier included in a convolution operator into sub-multipliers based on the precision of the feature map operands and the precision of the weight operands, performing the convolution operation between the feature map operands and the weight operands by using the decomposed sub-multipliers, each operand being processed in a sub-multiplier corresponding to a precision of the operand, and obtaining output feature maps corresponding to results of the convolution operation.

公开(公告)号：US20240095532A1

公开(公告)日：2024-03-21

申请号：US18522982

申请日：2023-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsun PARK ,  Yoojin KIM ,  Hyeongseok YU ,  Sehwan LEE ,  Junwoo JANG

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: A method of processing data includes identifying a sparsity among information, included in input data, based on valid information or invalid information included in the input data, rearranging the input data based on the sparsity among the information indicating a distribution of the invalid values included in the input data, and generating, by performing an operation on the rearranged input data in the neural network, an output data.