公开(公告)号：US20240047296A1

公开(公告)日：2024-02-08

申请号：US18229824

申请日：2023-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongbeom Ko ,  Junyun Kweon ,  Wonil Seo

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3677 ,  H01L23/3128 ,  H01L24/16 ,  H01L23/49833 ,  H01L2224/16225 ,  H01L25/18

Abstract: A semiconductor package includes a first semiconductor chip, a lower redistribution structure electrically connected to the first semiconductor chip, an upper redistribution structure on the first semiconductor chip, a conductive post electrically connecting the upper redistribution structure to the lower redistribution structure, and a first wire connecting a lower surface of the first semiconductor chip with an upper surface of the lower redistribution structure to dissipate heat of the first semiconductor chip.

公开(公告)号：US11854893B2

公开(公告)日：2023-12-26

申请号：US17850714

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Jumyong Park ,  Solji Song ,  Dongjoon Oh ,  Chungsun Lee ,  Hyunsu Hwang

IPC: H01L21/78 ,  H01L21/02 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/0206 ,  H01L24/80 ,  H01L24/94 ,  H01L24/97 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/97

Abstract: A method of manufacturing a semiconductor package, includes forming a mask layer on a wafer, the wafer including a semiconductor substrate and an insulating layer; forming a groove in the semiconductor substrate by performing a first laser grooving process; expanding an opening of the mask layer opened by the first laser grooving process by performing a second laser grooving process; exposing a portion of the insulating layer by removing a portion of the mask layer; and cutting the semiconductor substrate while removing the portion of the insulating layer exposed during the exposing by performing a dicing process.

公开(公告)号：US20230395547A1

公开(公告)日：2023-12-07

申请号：US18205329

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junyun Kweon ,  Yeongbeom Ko ,  Wooju Kim ,  Jungseok Ryu ,  Junho Yoon ,  Hwayoung Lee

IPC: H01L23/00 ,  H10B80/00

CPC classification number: H01L24/08 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes a first chip structure including a wiring structure disposed on a circuit elements, and first bonding metal layers and a first bonding insulating layer on the wiring structure, an upper surface of the first chip structure having an edge region and an inner region surrounded by the edge region, a second chip structure disposed on an inner region of the upper surface of the first chip structure, and including second bonding metal layers respectively bonded to the first bonding metal layers, a second bonding insulating layer bonded to the first bonding insulating layer, and a memory cell layer on the second bonding metal layers and the second bonding insulating layer, an insulating capping layer disposed on an upper surface of the second chip structure and extending to the edge region, and a connection pad disposed on a region of the insulating capping layer.

公开(公告)号：US20220037255A1

公开(公告)日：2022-02-03

申请号：US17210044

申请日：2021-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Hwang ,  Junyun Kweon ,  Jumyong Park ,  Jin Ho An ,  Dongjoon Oh ,  Chungsun Lee ,  Ju-il Choi

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/10 ,  H01L21/48

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package includes a redistribution substrate including redistribution line patterns in a dielectric layer, and a semiconductor chip on the redistribution substrate. The semiconductor chip includes chip pads electrically connected to the redistribution line patterns. Each of the redistribution line patterns has a substantially planar top surface and a nonplanar bottom surface. Each of the redistribution line patterns includes a central portion and edge portions on opposite sides of the central portion. Each of the redistribution line patterns has a first thickness as a minimum thickness at the central portion and a second thickness as a maximum thickness at the edge portions.