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公开(公告)号：US20240363603A1
公开(公告)日：2024-10-31
申请号：US18413248
申请日：2024-01-16
发明人： Chang LIANG , Zhigang DUAN , Jubao ZHANG
IPC分类号： H01L25/16 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/522
CPC分类号： H01L25/16 , H01L23/3121 , H01L23/49833 , H01L23/49838 , H01L23/5223 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/19041
摘要： A semiconductor package structure includes a first redistribution layer, a capacitor structure, and a second redistribution layer. The capacitor structure is disposed over the first redistribution layer and includes a semiconductor substrate, a first capacitor cell, a second capacitor cell, and a through via. The first capacitor cell and the second capacitor cell are disposed over the semiconductor substrate and separated by a first scribe line region. The through via is disposed in the first scribe line region. The second redistribution layer is disposed over the capacitor structure and is electrically coupled to the first redistribution layer through the through via.
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公开(公告)号：US20240363547A1
公开(公告)日：2024-10-31
申请号：US18308866
申请日：2023-04-28
发明人： Chien-Yuan HUANG , Chuei-Tang Wang , Shih-Chang Ku
IPC分类号： H01L23/00 , H01L23/367 , H01L25/00 , H01L25/065
CPC分类号： H01L23/562 , H01L23/367 , H01L25/0655 , H01L25/50 , H01L23/49816 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253
摘要： A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip package over and electrically connected to the wiring substrate. The chip package structure includes a first anti-warpage structure bonded to the wiring substrate. The first anti-warpage structure is made of a semiconductor material and electrically insulated from a wiring structure of the wiring substrate and the chip package. The chip package structure includes a heat dissipation structure over the wiring substrate and surrounding the chip package and the first anti-warpage structure.
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3.发明授权公开(公告)号：US12131796B2
公开(公告)日：2024-10-29
申请号：US18195860
申请日：2023-05-10
申请人： Rambus Inc.
发明人： Yohan Frans
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C7/22 , H01L25/065
CPC分类号： G11C7/10 , G11C5/02 , G11C5/063 , G11C7/22 , G11C5/025 , H01L25/0657 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/4824 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311
摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
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公开(公告)号：US20240356197A1
公开(公告)日：2024-10-24
申请号：US18137391
申请日：2023-04-20
发明人： Yuanhao YU , Weifan WU , Yong-Chang SYU , Chung Ju YU
IPC分类号： H01Q1/22 , H01L23/498 , H01Q9/04 , H01Q21/00
CPC分类号： H01Q1/2283 , H01L23/49811 , H01Q9/0407 , H01Q21/00 , H01L24/13 , H01L24/16 , H01L25/0655 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01Q9/0421
摘要： The present disclosure provides an electronic device, which includes an encapsulant, an electronic component, an antenna structure, and a first conductive element. The electronic component is disposed in the encapsulant. The antenna structure has an antenna pattern exposed to air and facing the encapsulant, and a first supporting element separating the antenna pattern from the encapsulant. At least a portion of the first conductive element is within the encapsulant, and electrically connects the antenna pattern to the electronic component by the first supporting element.
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公开(公告)号：US20240355803A1
公开(公告)日：2024-10-24
申请号：US18757882
申请日：2024-06-28
发明人： Han-Tang HUNG , Ming-Han LEE , Shau-Lin SHUE , Shin-Yi YANG
CPC分类号： H01L25/18 , H01L21/78 , H01L23/3107 , H01L23/485 , H01L23/585 , H01L24/16 , H01L25/50 , H01L2224/16225
摘要： Embodiments of the present disclosure provide a method for manufacturing a semiconductor package. The method includes providing a first integrated circuit (IC) die, wherein the first IC die has a first back-end-of-the-line (BEOL) structure. The method includes providing a first guard ring, wherein the first guard ring is disposed to encircle conductive features of the first BEOL. The method includes providing a second IC die, wherein the second IC die has a second BEOL structure, providing a second guard ring, wherein the second guard ring is disposed to encircle conductive features of the second BEOL. The method further includes providing an integrated BEOL structure, wherein a first side of the integrated BEOL structure is in direct contact with the first BEOL structure and the second BEOL structure.
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公开(公告)号：US20240355691A1
公开(公告)日：2024-10-24
申请号：US18761238
申请日：2024-07-01
发明人： Chun-Cheng Lin , Ching-Hua Hsieh , Chen-Hua Yu , Chung-Shi Liu , Chih-Wei Lin
IPC分类号： H01L23/31 , B29C45/14 , B29K63/00 , B29L31/34 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/29 , H01L23/367 , H01L23/498 , H01L23/538 , H01L25/065
CPC分类号： H01L23/3114 , H01L21/4853 , H01L21/486 , H01L21/565 , H01L21/566 , H01L23/295 , H01L23/3121 , H01L23/3135 , H01L23/3675 , H01L23/49816 , H01L23/5384 , H01L23/5385 , H01L23/5386 , H01L24/16 , H01L24/32 , H01L24/33 , H01L24/73 , H01L24/81 , H01L24/95 , H01L25/0655 , B29C45/14655 , B29K2063/00 , B29K2995/0007 , B29L2031/3406 , H01L24/13 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/13118 , H01L2224/1312 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13149 , H01L2224/13155 , H01L2224/16225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/81192 , H01L2924/1431 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19101 , H01L2924/3511
摘要： A semiconductor package including a circuit substrate, an interposer structure, a plurality of dies, and an insulating encapsulant is provided. The interposer structure is disposed on the circuit substrate. The plurality of dies is disposed on the interposer structure, wherein the plurality of dies is electrically connected to the circuit substrate through the interposer structure. The insulating encapsulant is disposed on the circuit substrate, wherein the insulating encapsulant surrounds the plurality of dies and the interposer structure and encapsulates at least the interposer structure, the insulating encapsulant has a groove that surrounds the interposer structure and the plurality of dies, and the interposer structure and the plurality of dies are confined to be located within the groove.
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公开(公告)号：US20240347493A1
公开(公告)日：2024-10-17
申请号：US18383512
申请日：2023-10-25
发明人： Wei-Hsin Wu , Ku-Pang Chang , Chun-Chia Yeh
IPC分类号： H01L23/00 , H01L23/498 , H05K1/11
CPC分类号： H01L24/16 , H01L23/49838 , H01L24/08 , H05K1/118 , H01L2224/0801 , H01L2224/08225 , H01L2224/16012 , H01L2224/16225 , H01L2924/3511 , H01L2924/384
摘要： A semiconductor package includes a flexible circuit board and a chip which includes a first bump group and a second bump group. First bumps of the first bump group and second bumps of the second bump group are provided to be bonded to leads on the flexible circuit board. The second bumps are designed to be longer than the first bumps in length so as to increase bonding strength of the second bumps to the leads, prevent the leads from being shifted and separated from the first and second bumps and prevent lead bonding misalignment.
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公开(公告)号：US20240347487A1
公开(公告)日：2024-10-17
申请号：US18368640
申请日：2023-09-15
发明人： Jaeean Lee , Dahee Kim , Taehoon Lee , Gyujin Choi
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498
CPC分类号： H01L24/05 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L24/06 , H01L24/08 , H01L23/49838 , H01L24/03 , H01L24/16 , H01L24/32 , H01L24/48 , H01L24/73 , H01L2224/03462 , H01L2224/05548 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/0601 , H01L2224/08225 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48225 , H01L2224/73265 , H01L2924/1815
摘要： An upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. The bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.
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公开(公告)号：US12119238B2
公开(公告)日：2024-10-15
申请号：US16588588
申请日：2019-09-30
发明人： Meng-Tse Chen , Hsiu-Jen Lin , Wei-Hung Lin , Kuei-Wei Huang , Ming-Da Cheng , Chung-Shi Liu
IPC分类号： H01L21/56 , H01L23/00 , H01L25/00 , H01L25/065 , H01L25/10
CPC分类号： H01L21/563 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/06181 , H01L2224/1144 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13111 , H01L2224/13124 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13172 , H01L2224/1403 , H01L2224/14181 , H01L2224/14505 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73204 , H01L2224/81203 , H01L2224/8123 , H01L2224/81815 , H01L2224/83191 , H01L2224/83192 , H01L2224/83855 , H01L2224/94 , H01L2224/97 , H01L2225/06513 , H01L2225/1023 , H01L2225/1058 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/15787 , H01L2924/181 , H01L2924/15787 , H01L2924/00 , H01L2924/181 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2224/94 , H01L2224/81 , H01L2224/13111 , H01L2924/013 , H01L2924/00014 , H01L2224/13147 , H01L2924/00014 , H01L2224/13166 , H01L2924/00014 , H01L2224/13172 , H01L2924/00014 , H01L2224/13124 , H01L2924/00014 , H01L2224/13155 , H01L2924/00014 , H01L2224/97 , H01L2224/81 , H01L2224/94 , H01L2224/11
摘要： A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.
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公开(公告)号：US20240339936A1
公开(公告)日：2024-10-10
申请号：US18748045
申请日：2024-06-19
发明人： Uwe Waltrich , Stanley Buchert , Marco Bohlländer , Claus Müller
IPC分类号： H02M7/00 , H01L23/00 , H01L23/31 , H01L23/498 , H02M7/537
CPC分类号： H02M7/003 , H01L23/3121 , H01L23/49822 , H01L24/16 , H01L24/32 , H01L24/73 , H02M7/537 , H01L2224/16225 , H01L2224/32225 , H01L2224/73253
摘要： A power electronics converter includes a substrate and a converter commutation cell including a power circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is comprised in a power semiconductor prepackage. An electrical connection side of the respective power semiconductor prepackage is spaced apart in a z direction from the substrate so as to define a prepackage gap between the substrate and the electrical connection side. At least a portion of the prepackage gap is filled with an electrically insulating material having voids. A converter parameter σ defined as an insulation fill factor divided by a maximum void size is greater than or equal to 10/mm. The insulation fill factor is defined as a cumulated volume of the voids subtracted from a volume of the electrically insulating material divided by the volume of the electrically insulating material.
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