公开(公告)号：US20240014049A1

公开(公告)日：2024-01-11

申请号：US18124255

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulho Jung ,  Jihan Ko ,  Kunsil Lee

IPC: H01L21/56 ,  H01L21/67

CPC classification number: H01L21/566 ,  H01L21/67126

Abstract: A release film for a mold process capable of minimizing defects of a semiconductor package in a semiconductor packaging process, and a method for manufacturing the release film for a mold process are provided. The release film for the mold process includes a base film and a plurality of conductive fillers located inside the base film and arranged on upper and/or lower surfaces of the base film, wherein roughness is formed by the plurality of conductive fillers on the upper and/or lower surfaces of the base film, and a conductive path is formed between the upper and lower surfaces of the base film.

公开(公告)号：US11631608B2

公开(公告)日：2023-04-18

申请号：US17060800

申请日：2020-10-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kunsil Lee ,  Seung Hwan Lee

IPC: H01L21/683 ,  H01L21/56 ,  H01L23/544 ,  H01L23/31 ,  H01L21/78

Abstract: Disclosed are support substrates, methods of fabricating semiconductor packages using the same, and methods of fabricating electronic devices using the same. The support substrate comprises a main body, and a plurality of first protrusions finely protruding from an upper surface of the main body. The main body and the first protrusions include the same material and are formed as a unitary structure. The first protrusions are spaced apart from each other in first and second directions intersecting each other, when viewed in plan.

公开(公告)号：US20190206844A1

公开(公告)日：2019-07-04

申请号：US16298083

申请日：2019-03-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kunsil Lee

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an upper portion of the first semiconductor chip, a second semiconductor chip on an upper surface of the first semiconductor chip and being electrically connected to the first semiconductor chip through the through silicon via of the first semiconductor chip, and an insulating bonding layer between the first semiconductor chip and the second semiconductor chip. The insulating bonding layer fills the first trench portion.