FLIP-FLOP LAYOUT ARCHITECTURE IMPLEMENTATION FOR SEMICONDUCTOR DEVICE
    12.
    发明申请
    FLIP-FLOP LAYOUT ARCHITECTURE IMPLEMENTATION FOR SEMICONDUCTOR DEVICE 有权
    用于半导体器件的FLIP-FLOP布局架构实现

    公开(公告)号:US20150179646A1

    公开(公告)日:2015-06-25

    申请号:US14504075

    申请日:2014-10-01

    Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

    Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上,第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极,并且连接线设置在连接触头上以与连接触头交叉,并将第一栅电极连接到第四栅电极。

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