公开(公告)号：US20170053917A1

公开(公告)日：2017-02-23

申请号：US15174036

申请日：2016-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： RAHEEL AZMAT ,  DEEPAK SHARMA ,  SU-HYEON KIM ,  CHULHONG PARK

IPC: H01L27/092 ,  H01L23/528 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/775 ,  H01L2027/11859

Abstract: Provided is a semiconductor device including a substrate with first, second, and third logic cells, active patterns provided in each of the first to third logic cells to protrude from the substrate, and gate structures crossing the active patterns. The second and third logic cells are spaced apart from each other in a first direction with the first logic cell interposed therebetween. The active patterns are arranged in the first direction and extend in a second direction crossing the first direction. When measured in the first direction, a distance between the closest adjacent pair of the active patterns with each in the first and second logic cells respectively is different from that between the closest pair of the active patterns with each in the first and third logic cells respectively.

Abstract translation: 提供了一种半导体器件，其包括具有第一，第二和第三逻辑单元的衬底，设置在从衬底突出的第一至第三逻辑单元中的每一个中的有源图案以及与有源图案交叉的栅极结构。 第二和第三逻辑单元在第一方向彼此间隔开，第一逻辑单元插入其间。 有源图案沿第一方向布置并且沿与第一方向交叉的第二方向延伸。 当在第一方向上测量时，分别在第一和第二逻辑单元中的最接近的活动图案对之间的距离分别与第一和第三逻辑单元中最近的一对活动图案之间的距离不同 。

公开(公告)号：US20180130786A1

公开(公告)日：2018-05-10

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHARMA DEEPAK ,  RAJEEV RANJAN ,  KUCHANURI SUBHASH ,  CHULHONG PARK ,  JAESEOK YANG ,  KWANYOUNG CHUN

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US20180129773A1

公开(公告)日：2018-05-10

申请号：US15610751

申请日：2017-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  CHULHONG PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L21/8234 ,  H01L27/02

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  H01L21/823437 ,  H01L27/0207

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.

公开(公告)号：US20170229478A1

公开(公告)日：2017-08-10

申请号：US15496015

申请日：2017-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

IPC: H01L27/118 ,  H01L29/06 ,  H01L23/535

CPC classification number: H01L27/11807 ,  H01L23/535 ,  H01L23/5384 ,  H01L27/0207 ,  H01L29/0649 ,  H01L2924/0002 ,  H03K19/1736 ,  H01L2924/00

Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.

公开(公告)号：US20150179646A1

公开(公告)日：2015-06-25

申请号：US14504075

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  RWIK SENGUPTA ,  CHULHONG PARK ,  KWANYOUNG CHUN

IPC: H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823871 ,  H01L27/0207

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions. First and second gate electrodes are provided on the PMOSFET region, and third and fourth gate electrodes are provided on the NMOSFET region. A connection contact is provided to connect the second gate electrode with the third gate electrode, and a connection line is provided on the connection contact to cross the connection contact and connect the first gate electrode to the fourth gate electrode.

Abstract translation: 半导体器件包括包括PMOSFET和NMOSFET区域的衬底。 第一和第二栅电极设置在PMOSFET区上，第三和第四栅电极设置在NMOSFET区上。 提供连接触点以连接第二栅电极和第三栅电极，并且连接线设置在连接触头上以与连接触头交叉，并将第一栅电极连接到第四栅电极。