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    INTEGRATED CIRCUIT DEVICES
    1.
    发明申请
    INTEGRATED CIRCUIT DEVICES 审中-公开

    公开(公告)号：US20190326285A1

    公开(公告)日：2019-10-24

    申请号：US16453645

    申请日：2019-06-26

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sidharth RASTOGI ,  Subhash KUCHANURI ,  Raheel AZMAT ,  Pan-jae PARK ,  Chul-hong PARK ,  Jae-seok YANG ,  Kwan-young CHUN

    IPC: H01L27/092 ,  H01L27/02 ,  H01L29/49 ,  H01L29/06 ,  H01L23/535 ,  H01L21/768 ,  H01L21/76

    Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY
    3.
    发明申请
    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY 审中-公开

    公开(公告)号：US20200294999A1

    公开(公告)日：2020-09-17

    申请号：US16887331

    申请日：2020-05-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

    IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY
    4.
    发明申请
    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY 审中-公开
    集成电路和标准单元库

    公开(公告)号：US20170033101A1

    公开(公告)日：2017-02-02

    申请号：US15060829

    申请日：2016-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

    IPC: H01L27/088 ,  H01L23/528 ,  H01L27/02

    CPC classification number: H01L27/0886 ,  H01L21/823828 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/6681

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

    Abstract translation: 提供了包括至少一个单元的集成电路，所述至少一个单元包括彼此间隔开的第一和第二有源区，设置在第一和第二有源区之间的虚拟区，设置在第一和第二有源区中的至少一个第一有源鳍 有源区并且在第一方向上延伸，在第二有源区的整个长度上沿着第一方向延伸的至少一个第二有源鳍，以及沿基本上垂直于第一方向的第二方向延伸的有源栅极线，其中 有源栅极线垂直地与第一有源区和虚拟区重叠，并且不垂直地与第二有源区重叠。

    SEMICONDUCTOR DEVICE
    5.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210057411A1

    公开(公告)日：2021-02-25

    申请号：US16864260

    申请日：2020-05-01

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20160099243A1

    公开(公告)日：2016-04-07

    申请号：US14736441

    申请日：2015-06-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Raheel AZMAT ,  Sharma DEEPAK ,  Chulhong PARK

    IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

    Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

    Abstract translation: 半导体器件及其制造方法包括在与第一方向相交的第二方向上在第一方向上延伸并彼此间隔开的第一和第二栅极结构，设置在第一和第二栅极结构之间的虚拟栅极结构 在第一栅极结构和伪栅极结构之间的第一源极/漏极区域，在第二栅极结构和伪栅极结构之间的第二源极/漏极区域，设置在虚拟栅极结构上的连接接触点以及公共导线 提供在连接接点上。 虚拟栅极结构沿第一方向延伸。 连接触头沿第二方向延伸以将第一源极/漏极区域连接到第二源极/漏极区域。 所述公共导线被配置为通过所述连接触点对所述第一和第二源/漏区的电压。

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220271034A1

    公开(公告)日：2022-08-25

    申请号：US17740900

    申请日：2022-05-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Taehyung KIM ,  Jinwoo JEONG ,  Jiwook KWON ,  Raheel AZMAT ,  Kwanyoung CHUN

    IPC: H01L27/092 ,  H01L23/528 ,  H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/02

    Abstract: A semiconductor device including a substrate; first to third active patterns on an upper portion of the substrate, the active patterns being sequentially arranged in a first direction and extending in a second direction crossing the first direction; first to third power rails respectively connected to the first to third active patterns, wherein a width of the second active pattern in the first direction is at least two times a width of the first active pattern in the first direction and is at least two times a width of the third active pattern in the first direction, the first active pattern is not vertically overlapped with the first power rail, the second active pattern is vertically overlapped with the second power rail, and the third active pattern is not vertically overlapped with the third power rail.

    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY
    10.
    发明申请
    INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY 审中-公开

    公开(公告)号：US20200303374A1

    公开(公告)日：2020-09-24

    申请号：US16894045

    申请日：2020-06-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Deepak SHARMA ,  Hyun-jong LEE ,  Raheel AZMAT ,  Chul-hong PARK ,  Sang-jun PARK

    IPC: H01L27/088 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L29/66

    Abstract: Provided is an integrated circuit including at least one cell, the at least one cell includes first and second active regions spaced apart from each other, a dummy region disposed between the first and second active regions, at least one first active fin disposed in the first active region and extending in a first direction, at least one second active fin extending along the first direction over the entire length of the second active region, and an active gate line extending in a second direction that is substantially perpendicular to the first direction, wherein the active gate line vertically overlaps the first active region and the dummy region and does not vertically overlap the second active region.

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