公开(公告)号：US10599410B2

公开(公告)日：2020-03-24

申请号：US15373443

申请日：2016-12-08

Applicant: Samsung Electronics Co., Ltd

Inventor： Young Sik Kim ,  In Ku Kang ,  Yu Seung Kim ,  Tae Hyun Kim ,  Dong Ho Jang ,  Eun Jung Hyun

IPC: H04L29/08 ,  G06F8/61 ,  G06F8/65 ,  G06F8/38 ,  H04L29/06 ,  H04W4/50 ,  H04L12/911 ,  H04L12/24

Abstract: An electronic device includes a communication circuit that communicates with an external device, a memory configured to store first setting data corresponding to a first time period, and a processor operatively connected with the communication circuit and the memory. The processor receives second setting data corresponding to a second time period from the external device through the communication circuit if a specified time point is reached, deletes at least a portion of the first setting data based on whether a status of a user is a login status or a logout status, and applies the second setting data to the electronic device.

公开(公告)号：US10445014B2

公开(公告)日：2019-10-15

申请号：US15676651

申请日：2017-08-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hee Hyun Nam ,  Young Sik Kim ,  Jin Woo Kim ,  Young Jo Park ,  Jae Geun Park ,  Young Jin Cho

IPC: G06F3/06

Abstract: A method of operating a memory controller is provided. The method of operating a memory controller according to an exemplary embodiment of the present inventive concepts includes sequentially receiving, by the memory controller, first data segments each having a first size from a host, sequentially storing, by the memory controller, the first data segments in the buffer until a sum of sizes of changed data among data stored in a buffer included in the memory controller is a second size, and programming, by the memory controller, the changed data having the second size in a memory space of a non-volatile memory as a second data segment.

公开(公告)号：US20190244932A1

公开(公告)日：2019-08-08

申请号：US15995176

申请日：2018-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doo Jin Kim ,  Young Sik Kim

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip disposed on a substrate. A first upward pad is disposed on an upper surface of the first semiconductor chip. A second semiconductor chip is arranged with an offset above the first semiconductor chip. A first downward pad is disposed on a lower surface of the second semiconductor chip. A first bonding wire connects the first upward pad and the substrate. A first inter-chip connector is interposed between the first upward pad and the first downward pad. A side surface of the second semiconductor chip is arranged above the first upward pad.

公开(公告)号：US09935942B2

公开(公告)日：2018-04-03

申请号：US15010027

申请日：2016-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Hyun Kim ,  Young Sik Kim ,  Yu Seung Kim ,  Dong Ho Jang

IPC: H04L29/06 ,  G06F21/36 ,  H04W12/06

CPC classification number: H04L63/083 ,  G06F21/36 ,  H04W12/06

Abstract: An electronic device and authentication processing method for operating the electronic device is provided. The authentication processing method includes transmitting to an external server credential information input in the electronic device through a user interface, receiving an authentication request of the credential information, processing the authentication request based on the credential information stored in the electronic device, or determining whether to transmit the authentication request through the communication module based on the credential information stored in the external server.

公开(公告)号：US20130097386A1

公开(公告)日：2013-04-18

申请号：US13652894

申请日：2012-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Industry-Academia Cooperation Group of Sejong University

Inventor： Won Jong LEE ,  Sang Oak Woo ,  Seok Yoon Jung ,  Woo Chan Park ,  Young Sik Kim

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F12/126 ,  G06T1/60 ,  Y02D10/13

Abstract: A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.

Abstract translation: 可以提供用于基于瓦片的呈现的高速缓冲存储器系统和缓存方法。 缓存存储器系统中的每个高速缓存行可以包括延迟替换信息。 延迟替换信息可以指示在高速缓存行中是否包括在瓦片的边缘的位置处引用的纹理数据。 当高速缓冲存储器系统中不存在对应于访问请求地址的高速缓存行时，高速缓冲存储器系统可以基于延迟替换信息来从关联高速缓存单元中选择和移除要移除的高速缓存行。