TEXTURE CACHE MEMORY SYSTEM OF NON-BLOCKING FOR TEXTURE MAPPING PIPELINE AND OPERATION METHOD OF TEXTURE CACHE MEMORY
    3.
    发明申请
    TEXTURE CACHE MEMORY SYSTEM OF NON-BLOCKING FOR TEXTURE MAPPING PIPELINE AND OPERATION METHOD OF TEXTURE CACHE MEMORY 有权
    用于纹理映射管道的非阻塞纹理缓存存储器系统和纹理缓存存储器的操作方法

    公开(公告)号:US20140244939A1

    公开(公告)日:2014-08-28

    申请号:US13966889

    申请日:2013-08-14

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0875 G06F12/0855

    摘要: A non-blocking texture cache memory for a texture mapping pipeline and an operation method of the non-blocking texture cache memory may include: a retry buffer configured to temporarily store result data according to a hit pipeline or a miss pipeline; a retry buffer lookup unit configured to look up the retry buffer in response to a texture request transferred from a processor; a verification unit configured to verify whether result data corresponding to the texture request is stored in the retry buffer as the lookup result; and an output control unit configured to output the stored result data to the processor when the result data corresponding to the texture request is stored as the verification result.

    摘要翻译: 用于纹理映射流水线的非阻塞纹理缓存存储器和非阻塞纹理缓存存储器的操作方法可以包括:重试缓冲器,其被配置为根据命中管道或遗漏流水线临时存储结果数据; 重试缓冲器查找单元,被配置为响应于从处理器传送的纹理请求来查找重试缓冲器; 验证单元,被配置为验证与纹理请求相对应的结果数据是否作为查找结果存储在重试缓冲器中; 以及输出控制单元,被配置为当存储与纹理请求对应的结果数据作为验证结果时,将存储的结果数据输出到处理器。

    Electronic device and method for commonly using the same

    公开(公告)号:US10305883B2

    公开(公告)日:2019-05-28

    申请号:US15226228

    申请日:2016-08-02

    摘要: An electronic device and a method for commonly using the electronic device are provided. The electronic device includes a housing, a memory disposed in the housing, a communication circuit in communication with at least one external device, and a processor electrically connected to the memory and the communication circuit. The processor is configured to control for installing at least one application on the memory in response to a login request from a user, receiving a logout request from the user after the at least one application is installed, transmitting data associated with the at least one application to the at least one external device using the communication circuit in response to the logout request, and deleting at least a portion of the at least one application and the data associated with the at least one application from the memory.

    Cache memory system for tile based rendering and caching method thereof
    6.
    发明授权
    Cache memory system for tile based rendering and caching method thereof 有权
    用于基于瓦片的呈现和缓存方法的缓存存储器系统

    公开(公告)号:US09176880B2

    公开(公告)日:2015-11-03

    申请号:US13652894

    申请日:2012-10-16

    IPC分类号: G06F12/08 G06F12/12 G06T1/60

    摘要: A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.

    摘要翻译: 可以提供用于基于瓦片的呈现的高速缓冲存储器系统和缓存方法。 缓存存储器系统中的每个高速缓存行可以包括延迟替换信息。 延迟替换信息可以指示在高速缓存行中是否包括在瓦片的边缘的位置处引用的纹理数据。 当高速缓冲存储器系统中不存在对应于访问请求地址的高速缓存行时,高速缓冲存储器系统可以基于延迟替换信息来从关联高速缓存单元中选择和移除要移除的高速缓存行。

    Semiconductor package including semiconductor chip

    公开(公告)号:US10714453B2

    公开(公告)日:2020-07-14

    申请号:US15995176

    申请日:2018-06-01

    摘要: A semiconductor package includes a first semiconductor chip disposed on a substrate. A first upward pad is disposed on an upper surface of the first semiconductor chip. A second semiconductor chip is arranged with an offset above the first semiconductor chip. A first downward pad is disposed on a lower surface of the second semiconductor chip. A first bonding wire connects the first upward pad and the substrate. A first inter-chip connector is interposed between the first upward pad and the first downward pad. A side surface of the second semiconductor chip is arranged above the first upward pad.

    Capillary exchange system of semiconductor wire bonding
    9.
    发明授权
    Capillary exchange system of semiconductor wire bonding 失效
    半导体引线接合毛细管交换系统

    公开(公告)号:US08672210B2

    公开(公告)日:2014-03-18

    申请号:US13728316

    申请日:2012-12-27

    IPC分类号: B23K37/00

    摘要: A capillary exchange system of a semiconductor wire bonding includes a wire bond unit having a chuck that includes a holding portion for holding a capillary for semiconductor wire bonding, a holding release guide unit for mechanically acting on the chuck of the wire bond unit to allow the capillary to be held by the holding portion or released from the holding portion, and a capillary exchange unit for separating the capillary from the chuck of the wire bond unit and installing a new capillary in the chuck in cooperation with the holding release guide unit.

    摘要翻译: 半导体引线接合的毛细管交换系统包括具有卡盘的引线接合单元,该卡盘包括用于保持用于半导体引线接合的毛细管的保持部分,用于机械地作用在引线接合单元的卡盘上的保持释放引导单元, 由保持部保持的毛细管或从保持部分释放的毛细管,以及毛细管交换单元,用于将毛细管与线接合单元的卡盘分离,并与保持释放引导单元配合地将新的毛细管安装在卡盘中。