公开(公告)号：US11250917B2

公开(公告)日：2022-02-15

申请号：US16910697

申请日：2020-06-24

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C16/24

Abstract: A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

公开(公告)号：US20200211652A1

公开(公告)日：2020-07-02

申请号：US16236792

申请日：2018-12-31

Applicant: SanDisk Technologies LLC

Inventor： Jianzhi Wu ,  Xiang Yang ,  Jun Wan

IPC: G11C16/16 ,  G11C29/00 ,  G06F3/06 ,  G06F12/02

Abstract: Example techniques that mitigate against memory hole shorts during an erase operation for memory cells in a string include an example method in which, during an erase operation, erase pulses are applied to the word lines of the memory string and terminated at different times based. In some instances, the erase pulses applied to the word lines of the memory string are terminated based on the temperature of the memory cells of the memory string. In further implementations, the erase pulses applied to the word lines of the memory string are boosted for different times depending on the location of the word line along the memory string during the erase operation.

公开(公告)号：US20190252030A1

公开(公告)日：2019-08-15

申请号：US15963647

申请日：2018-04-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta ,  Jianzhi Wu ,  Gerrit Jan Hemink

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24

Abstract: Disclosed herein is related to a memory device and a method of verifying a programmed status of the memory device. The memory device includes memory cells coupled to a word line. The memory device includes a controller coupled to the word line. The controller is configured to program the memory cells coupled to the word line. The controller is configured to verify a programmed status of a first subset of the memory cells coupled to the word line and a programmed status of a second subset of the memory cells coupled to the word line, based on the programmed status of the first subset of the memory cells.