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公开(公告)号：US20240212768A1
公开(公告)日：2024-06-27
申请号：US18357412
申请日：2023-07-24
发明人： Huiwen Xu , Deepanshu Dutta , Bo Lei
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/3404
摘要： A non-volatile memory system detects an indication of erase depth of a population of memory cells and adjusts the programming process for the memory cells based on the detected erase depth.
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公开(公告)号：US11972812B2
公开(公告)日：2024-04-30
申请号：US17549431
申请日：2021-12-13
发明人： Yi Song , Jiahui Yuan , Jun Wan , Deepanshu Dutta
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
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公开(公告)号：US20240029789A1
公开(公告)日：2024-01-25
申请号：US17870055
申请日：2022-07-21
发明人： Xiang Yang , Deepanshu Dutta
IPC分类号： G11C11/56 , G11C16/10 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
CPC分类号： G11C11/5671 , G11C11/5628 , G11C16/10 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573
摘要： The memory die that includes a plurality of memory blocks. Each memory block includes a plurality of memory cells that are configured to store three bits of data in each memory cell when the memory die is in a TLC operating mode. The memory die has a non-binary data capacity, which is a multiple of 683 Gb, when the memory die is operating in the TLC operating mode.
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公开(公告)号：US20230410911A1
公开(公告)日：2023-12-21
申请号：US17825321
申请日：2022-05-26
发明人： Towhidur Razzak , Jiahui Yuan , Deepanshu Dutta
CPC分类号： G11C16/10 , G11C16/0483 , H01L25/0657 , G11C16/3459 , G11C16/08
摘要： Technology is disclosed herein for a memory system that balances peak Icc with programming speed. A memory system applies voltages to respective word lines during a verify operation that balances peak Icc with programming speed. The voltages for which the ramp rate is controlled include a read pass voltage applied to unselected word lines and a spike voltage applied to the selected word line at the beginning of the verify. The ramp rate of the voltages is slow enough to keep the peak Icc during verify to a target peak Icc regardless of which word line is selected for verify. However, the ramp rate of the voltages to the word lines during verify is fast enough to make use of the target peak Icc in order achieve faster programming. Therefore, the impact on programming time is minimized while staying withing the allowed peak Icc.
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公开(公告)号：US20230307072A1
公开(公告)日：2023-09-28
申请号：US17701365
申请日：2022-03-22
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/10 , H01L27/11556
摘要： The memory device includes a controller that is configured to program the memory cells of a selected word line in a plurality of program-verify iterations. During a verify portion at least one of the program-verify iterations, the controller determines a threshold voltage of at least one memory cell relative to a first verify low voltage VL1, a second verify low voltage VL2, and a verify high voltage VH associated with a data state being programmed. The controller also maintains a count of program-verify iterations since the at least one memory cell passed a verify high voltage of a previously programmed data state or discharges a sense node through a channel including the at least one memory cell and compares a discharge time to predetermined sense times associated with the first and second verify low voltages and with the verify high voltage.
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公开(公告)号：US20230187000A1
公开(公告)日：2023-06-15
申请号：US17549431
申请日：2021-12-13
发明人： Yi Song , Jiahui Yuan , Jun Wan , Deepanshu Dutta
CPC分类号： G11C16/3459 , G11C16/3404 , G11C16/102 , G11C16/26 , G11C16/08
摘要： A memory system identifies memory cells connected to a common word line that have had their threshold voltage unintentionally drift lower than programmed by determining whether memory cells meet two criteria: (1) the memory cells have threshold voltages within an offset of a read compare voltage of a data state; and (2) adjacent memory cells (connected to word lines that are adjacent to the common word line) are in one or more low data states. For those memory cells meeting the two criteria, the memory system performs some amount of programming on the memory cells to refresh the data stored in those memory cells to be as originally intended.
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公开(公告)号：US20230146549A1
公开(公告)日：2023-05-11
申请号：US17522414
申请日：2021-11-09
发明人： Yu-Chung Lien , Deepanshu Dutta , Tai-Yuan Tseng
IPC分类号： G11C11/4096 , G11C11/408 , G11C11/4076 , G11C11/4074
CPC分类号： G11C11/4096 , G11C11/4087 , G11C11/4085 , G11C11/4076 , G11C11/4074
摘要： A memory device with one or more planes having sub-blocks is disclosed. The memory device may further include a voltage switch transistor for each of sub-blocks. Additionally, the memory device may further include a row decoder for each of sub-blocks. As a result, an operation to two sub-blocks can be performed at different times. For example, using a row decoder and voltage switch transistor, a sub-block can be initially read, followed by a subsequent read of another sub-block using a separate row decoder and voltage switch transistor. By staggering the read operations through a time delay, the peak current Icc associated with the supply voltage can be reduced.
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公开(公告)号：US20230076245A1
公开(公告)日：2023-03-09
申请号：US17469016
申请日：2021-09-08
发明人： Xiang Yang , Deepanshu Dutta , Gerrit Jan Hemink
摘要： An apparatus includes a control circuit configured to connect to first word lines of a first vertical sub-block and second word lines of a second vertical sub-block. The first vertical sub-block and the second vertical sub-block include memory cells connected in series in NAND strings, each NAND string including memory cells coupled to the first word lines in series with memory cells connected to the second word lines. The control circuit is configured to program or sense memory cells along a selected first word line of the first vertical sub-block while applying a first voltage to second word lines that are connected to programmed memory cells and applying a second voltage to second word lines that are connected to unprogrammed memory cells.
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公开(公告)号：US20220359017A1
公开(公告)日：2022-11-10
申请号：US17307396
申请日：2021-05-04
发明人： Sujjatul Islam , Ravi J. Kumar , Deepanshu Dutta
摘要： An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.
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公开(公告)号：US11417400B2
公开(公告)日：2022-08-16
申请号：US16778821
申请日：2020-01-31
发明人： Yu-Chung Lien , Huai-Yuan Tseng , Deepanshu Dutta
IPC分类号： G11C16/00 , G11C16/26 , H01L27/11556 , G11C5/06 , G11C16/10 , G11C5/02 , H01L27/11582
摘要： Techniques are described for optimizing the peak current during a program operation by controlling a timing and ramp rate of a program-inhibit voltage signal as a function of a program loop number and/or program progress. A transition voltage between a regulated ramp up rate and an unregulated ramp up rate can also be adjusted. For initial and final sets of program loops in a program operation, the ramp up of the program-inhibit voltage signal can occur early so that it overlaps with operations of sense circuits in updating their latches based on results from a verify test in a previous program loop. For an intermediate set of program loops, the overlap is avoided. The ramp up rate can be larger and the transition voltage smaller for the initial and final sets of program loops compared to the intermediate set of program loops.
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