公开(公告)号：US10275361B2

公开(公告)日：2019-04-30

申请号：US15609758

申请日：2017-05-31

Applicant: Seagate Technology LLC

Inventor： Mark Ish ,  Steven S. Williams ,  Jeffrey Munsil

IPC: G06F12/10

Abstract: Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

公开(公告)号：US10248330B2

公开(公告)日：2019-04-02

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F12/00 ,  G06F3/06

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

公开(公告)号：US20180341594A1

公开(公告)日：2018-11-29

申请号：US15606502

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.