公开(公告)号：US20180349035A1

公开(公告)日：2018-12-06

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

公开(公告)号：US20180349266A1

公开(公告)日：2018-12-06

申请号：US15609198

申请日：2017-05-31

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa ,  Ryan J. Goss ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/065 ,  G06F3/0655 ,  G06F3/0688 ,  G06F2212/7201

Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.

公开(公告)号：US10664168B2

公开(公告)日：2020-05-26

申请号：US16201767

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06 ,  G06F13/16

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

公开(公告)号：US20180341403A1

公开(公告)日：2018-11-29

申请号：US15606549

申请日：2017-05-26

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

公开(公告)号：US09905294B1

公开(公告)日：2018-02-27

申请号：US15585429

申请日：2017-05-03

Applicant: Seagate Technology, LLC

Inventor： Timothy L. Canepa ,  Alex Tang ,  Stephen Hanna

IPC: G11C16/04 ,  G11C11/56 ,  G11C13/00 ,  G06F12/02 ,  G11C16/24 ,  G11C16/26 ,  G06F13/40

CPC classification number: G11C11/5642 ,  G06F12/0246 ,  G06F13/4004 ,  G11C11/5628 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: Method and apparatus for managing data in a data storage device. In some embodiments, a non-volatile cache memory stores a sequence of pages from a host device. A non-volatile main memory has a plurality of n-level cells arranged on m separate integrated circuit dies each simultaneously accessible during programming and read operations using an associated transfer circuit, where m and n are plural numbers. A control circuit writes first and second pages from the sequence of pages to a selected set of the n-level cells coupled to a common word line on a selected integrated circuit die. The second page is separated from the first page in the sequence of pages by a logical offset comprising a plurality of intervening pages in the sequence of pages. The logical offset is selected responsive to the m number of integrated circuit dies and a delay time associated with the transfer circuits.

公开(公告)号：US10229052B2

公开(公告)日：2019-03-12

申请号：US15609198

申请日：2017-05-31

Applicant: Seagate Technology, LLC

Inventor： Timothy Canepa ,  Ryan J. Goss ,  Stephen Hanna

IPC: G06F12/02 ,  G06F3/06

Abstract: Method and apparatus for managing data such as in a flash memory. In some embodiments, a memory module electronics (MME) circuit writes groups of user data blocks to consecutive locations within a selected section of a non-volatile memory (NVM), and concurrently writes a directory map structure as a sequence of map entries distributed among the groups of user data blocks. Each map entry stores address information for the user data blocks in the associated group and a pointer to a subsequent map entry in the sequence. A control circuit accesses a first map entry in the sequence and uses the address information and pointer in the first map entry to locate the remaining map entries and the locations of the user data blocks in the respective groups. Lossless data compression may be applied to the groups prior to writing.

公开(公告)号：US20180046543A1

公开(公告)日：2018-02-15

申请号：US15232058

申请日：2016-08-09

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F11/10 ,  H03M13/15 ,  G11C16/22 ,  G11C29/52 ,  G11C11/56 ,  G11C16/14

CPC classification number: G06F11/1072 ,  G06F2212/7207 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/14 ,  G11C16/22 ,  G11C29/52 ,  G11C2211/5641 ,  H03M13/11 ,  H03M13/154

Abstract: Methods and structure for preventing lower page corruption in flash memory. One embodiment is a flash storage device that includes Multi-Level Cell (MLC) flash memory, Single-Level Cell (SLC) flash memory, and a controller coupled to the MLC flash memory and the SLC flash memory. The controller is configured to program host data to a lower page of the MLC flash memory, to generate an erasure code for the host data, and to store the erasure code in the SLC flash memory. The controller is also configured to detect an interrupted write operation to an upper page linked to the lower page, to retrieve the erasure code from the SLC flash memory, and to correct the host data of the lower page of the MLC flash memory using the erasure code.

公开(公告)号：US10353622B2

公开(公告)日：2019-07-16

申请号：US15448103

申请日：2017-03-02

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Erich F. Haratsch ,  Zhengang Chen ,  Stephen Hanna ,  Abdelhakim Alhussien

IPC: H03M13/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  H03M13/37 ,  H03M13/11 ,  H03M13/15

Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.

公开(公告)号：US10248330B2

公开(公告)日：2019-04-02

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F12/00 ,  G06F3/06

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

公开(公告)号：US20190095099A1

公开(公告)日：2019-03-28

申请号：US16201767

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06 ,  G06F12/02

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.