公开(公告)号：US11630779B2

公开(公告)日：2023-04-18

申请号：US17528977

申请日：2021-11-17

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US20190095341A1

公开(公告)日：2019-03-28

申请号：US16201733

申请日：2018-11-27

Applicant: Seagate Technology LLC

Inventor： Timothy Canepa ,  Jeffrey Munsil ,  Jackson Ellis ,  Mark Ish

IPC: G06F12/1009 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0613 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7208

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

公开(公告)号：US20220075729A1

公开(公告)日：2022-03-10

申请号：US17528977

申请日：2021-11-17

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US10740251B2

公开(公告)日：2020-08-11

申请号：US15411679

申请日：2017-01-20

Applicant: Seagate Technology LLC

Inventor： Alex Tang ,  Leonid Baryudin ,  Timothy Canepa ,  Jackson Ellis

IPC: G06F12/128 ,  G06F12/02 ,  G06F12/0868 ,  G06F12/0888

Abstract: The implementations described herein provide a hybrid drive with a storage capacity including solid-state drive (NAND) technology and hard disc drive (HDD) technology. A translation layer is stored in the solid-state drive and includes plurality of entries. Each entry of the plurality of entries corresponds to at least one logical data unit and includes a cache state indicating where the data corresponding to the logical data unit is located and whether the data is valid. The translation layer may be a multi-layer map that includes a sparse mapping scheme. In a sparse multi-layer map, entries are leaf entries or non-leaf entries. Leaf entries include a cache state for the corresponding logical data unit(s). Non-leaf entries may include a pointer to a lower level mapping for a plurality of logical data units.

公开(公告)号：US20190050417A1

公开(公告)日：2019-02-14

申请号：US15671469

申请日：2017-08-08

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Carl Forhan

IPC: G06F17/30 ,  G06F3/06 ,  G06F21/78 ,  G06F21/62

Abstract: A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

公开(公告)号：US20180349035A1

公开(公告)日：2018-12-06

申请号：US15608203

申请日：2017-05-30

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil ,  Timothy Canepa ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

公开(公告)号：US11221956B2

公开(公告)日：2022-01-11

申请号：US15609651

申请日：2017-05-31

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US20190033374A1

公开(公告)日：2019-01-31

申请号：US15704515

申请日：2017-09-14

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Jackson Ellis ,  Mark von Gnechten

IPC: G01R31/3185 ,  G01R31/28 ,  G06F9/30 ,  G06F12/14

Abstract: A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

公开(公告)号：US20180349036A1

公开(公告)日：2018-12-06

申请号：US15610806

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Jackson Ellis ,  Jeffrey Munsil

IPC: G06F3/06 ,  G06F12/10

Abstract: A data storage device can be configured with a data map that has one or more custom map attributes. A non-volatile memory of the data storage device may store data organized into a data map by a mapping module. The data map consisting of at least a data address translation and a custom attribute pertaining to an operational parameter of the data map with the custom attribute generated and maintained by the mapping module.

公开(公告)号：US10126964B2

公开(公告)日：2018-11-13

申请号：US15605442

申请日：2017-05-25

Applicant: Seagate Technology LLC

Inventor： Jeffrey Munsil ,  Jackson Ellis ,  Ryan J. Goss

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0873 ,  G06F12/0811

Abstract: Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.