Abstract:
A method for driving a plasma display panel, including a reset period, an address period, and a sustain discharge period, wherein the reset period has a rising ramp section. During the rising ramp section of the reset period, a flat period of maintaining a peak voltage of a rising ramp applied to a scan electrode is maintained for longer than a period until a variation in a state of wall charges of the scan electrode is ended in all discharge cells.
Abstract:
A method of driving a plasma display panel having a discharge space formed by at least two electrodes is disclosed. In a reset period, the method includes changing a voltage of a first electrode by a first voltage to discharge the discharge space; floating the first electrode during a first period after changing the voltage of the first electrode by the first voltage; changing the voltage of the first electrode by a second voltage in a opposite direction of the first voltage after the first period; and floating the first electrode during the second period after changing the voltage of the first electrode by the second voltage. These steps may be repeated.
Abstract:
A plasma display panel (PDP) and a method for driving the PDP are described. A falling pulse waveform including alternately repeated voltage falling periods and floating periods that have a first mean slope and another falling pulse waveform including alternately repeated voltage falling periods and floating periods that have a second mean slope gentler than the first mean slope may be applied to sustain electrodes. The first and second slopes may be controlled by controlling the floating time or voltage falling range. In accordance with the present invention, it may be possible to apply pulse waveforms having diverse slopes through a simple driving circuit by floating a voltage charged in or discharged from a panel capacitor.
Abstract:
A PDP driving method. A falling ramp voltage is applied to a scan electrode so as to reset a state of wall charges of a discharge cell during a reset period. In this instance, a sustain electrode is maintained at a high voltage during an initial period for applying the falling ramp voltage, and the voltage at the sustain electrode is reduced to a normal voltage at a latter part of the period for applying the falling ramp voltage. Accordingly, the voltage applied to an address electrode is reduced in an address period since an erased amount of the wall charges of the address electrode is reduced during the reset period.
Abstract:
A PDP driving method. When a first sustain pulse is applied to a scan electrode during a sustain period, an address electrode is biased by a positive voltage, or the address electrode is biased. Therefore, when a large amount of wall charges are formed on the address and scan electrodes by address discharging during an address period, no main discharge is generated since a high potential of the address electrode is formed in the sustain period.
Abstract:
Disclosed are a driving device and a driving method for a plasma display panel (PDP). A panel capacitor is formed by a scan electrode and a sustain electrode. The charges are moved from the panel capacitor to a capacitor by turning on a transistor which is connected between the scan electrode and the capacitor. By this method, the voltage of the panel capacitor is steeply reduced so that a discharge is generated in the panel capacitor. When the voltage of the capacitor increases because of the charges moved from the panel capacitor, the gate-source voltage of the transistor is reduced. As a result, the transistor is turned off so that the scan electrode is floated. Accordingly, the discharge is steeply quenched so that the wall charges are precisely controlled. After the capacitor is discharged, the above-noted operation may be repeated.
Abstract:
A plasma display device including: a plasma display panel including a plurality of electrodes; a printed circuit board assembly (PBA) activating the plasma display panel (PDP); a chassis base, including: a first surface supporting the plasma display panel (PDP), and a second surface having the printed circuit board assembly (PBA); signal lines applying a voltage, a data signal, and a control signal to the electrodes are formed at the end of the plasma display panel (PDP); and an interface flexible printed circuit connecting the signal lines to the printed circuit board assembly (PBA), wherein at least one of the signal lines has a line width at a portion further from the interface flexible printed circuit (FPC) that is larger than a line width at a portion closer to the interface flexible printed circuit (FPC).
Abstract:
An initialization and driving method for a plasma display panel. When the plasma display panel is turned on, a voltage at a first electrode is increased from a first voltage to a second voltage, and a voltage at a second electrode is reduced from a fourth voltage to the fifth voltage for the purpose of forming wall charges in cells while a third voltage is applied to the second electrode. A voltage is applied to the first electrode and the second electrode to establish a difference between the first electrode and the second electrode to be alternately a sixth voltage and a negative voltage of the sixth voltage, and therefore the cell is discharged.
Abstract:
In a plasma display, image data are mapped on N subfields, and the subfield with the greatest weight is determined from among the mapped subfields. When the subfield with the greatest weight is the Kth subfield (K>M), grayscales of the image data are expressed with the mapped data of the (K−M+1)th subfield to the Kth subfield, and the mapped data from the first subfield to the (K−M)th subfield may be ignored.
Abstract:
A driving apparatus of a plasma display panel for applying a rising or falling waveform to a panel capacitor, comprising a transistor for forming a current path between a power source and the panel capacitor while the transistor is turned on, and which is coupled between the power source and one end of the panel capacitor. A first capacitor and a second capacitor are coupled in parallel to each other and in between a drain and a gate of the transistor. A first resistor and a first diode are coupled in parallel to each other between a first end of the first capacitor and the gate, and a second resistor and a second diode are coupled in parallel to each other between a first end of the second capacitor and the gate.