公开(公告)号：US5323352A

公开(公告)日：1994-06-21

申请号：US754764

申请日：1991-09-04

申请人： Souichi Miyata ,  Kouichi Hatakekyama ,  Tsuyoshi Muramatsu

发明人： Souichi Miyata ,  Kouichi Hatakekyama ,  Tsuyoshi Muramatsu

IPC分类号： G11C11/406 ,  G11C7/00

CPC分类号： G11C11/406

摘要： A refresh control circuit includes a refresh request generating circuit, a multiplexer, a memory access control circuit and an elimination control circuit. The refresh request generating circuit periodically outputs a transfer pulse and a refresh packet for refreshing. The merging control circuit receives a transfer pulse for normal access and a transfer pulse for refreshing. The merging control circuit, when the transfer pulse for refreshing and the transfer pulse for normal access contend with each other, applies first the transfer pulse to the memory access control circuit, makes the other stand by and generates an identification signal for identifying normal access and refreshing. The multiplexer receives a refresh packet and a data packet and applies one of the packets to the memory access control circuit in response to the identification signal. The memory access control circuit selectively controls a normal access operation based on the data packet or a refresh operation based on the refresh packet in response to the identification signal to output a transfer pulse. When an identification signal indicates a refresh operation, the elimination control circuit eliminates a transfer pulse output from the memory access control circuit.

摘要翻译： 刷新控制电路包括刷新请求生成电路，复用器，存储器访问控制电路和消除控制电路。 刷新请求生成电路周期性地输出用于刷新的传送脉冲和刷新包。 合并控制电路接收用于正常访问的传送脉冲和用于刷新的传送脉冲。 合并控制电路，当用于刷新的传送脉冲和用于正常访问的传送脉冲相互抵触时，首先将传送脉冲施加到存储器访问控制电路，使另一个备用并产生用于识别正常访问的识别信号， 清爽 复用器接收刷新分组和数据分组，并响应于识别信号将一个分组应用于存储器访问控制电路。 存储器访问控制电路响应于识别信号，选择性地基于数据包或基于刷新包的刷新操作来控制正常访问操作，以输出传送脉冲。 当识别信号指示刷新操作时，消除控制电路消除从存储器访问控制电路输出的传送脉冲。

公开(公告)号：US07483427B2

公开(公告)日：2009-01-27

申请号：US11052901

申请日：2005-02-09

申请人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

发明人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

IPC分类号： H04L12/28

CPC分类号： H04L47/10 ,  G06F9/4494

摘要： A branching control unit includes a logic gate and a NAND circuit that can receive transfer permission for each branching designation. The branching control unit further includes a transfer request unit receiving respective outputs of the logic gate and NAND circuit. The transfer request unit sends a data transfer request to a branching designation when the logic gate or NAND circuit is rendered active. Since transfer permission can be received for each branching designation to send a transfer request, a data waiting state depending upon the data holding state of another branching destination will no longer occur. Thus, a data driven type information processing apparatus and method of transferring a data packet at higher speed in a data transmission path can be provided.

摘要翻译： 分支控制单元包括可以接收每个分支指定的传送许可的逻辑门和NAND电路。 分支控制单元还包括接收逻辑门和NAND电路的各个输出的传送请求单元。 当逻辑门或NAND电路被激活时，传送请求单元将数据传送请求发送到分支指定。 由于可以为每个分支指定接收到传送许可以发送传送请求，所以将不再发生根据另一分支目的地的数据保持状态的数据等待状态。 因此，可以提供数据驱动型信息处理装置和在数据传输路径中以较高速度传输数据包的方法。

公开(公告)号：US07133959B2

公开(公告)日：2006-11-07

申请号：US10320555

申请日：2002-12-17

申请人： Kouichi Hatakeyama ,  Tsuyoshi Muramatsu

发明人： Kouichi Hatakeyama ,  Tsuyoshi Muramatsu

IPC分类号： G06F12/04

CPC分类号： G06F9/345

摘要： An address calculation unit calculates a plurality of addresses corresponding to a plurality of data included in a data packet. A first bank memory access unit accesses a first bank memory according to a first address calculated by the address calculation unit. Simultaneously, a second bank memory access unit accesses a second bank memory according to a second address calculated by the address calculation unit. A packet reconstruction unit reconstructs the data packet according to the results of access by the first and second bank memory access units. Accordingly the processing rate of the data packet including a plurality of data is increased.

公开(公告)号：US07082515B2

公开(公告)日：2006-07-25

申请号：US09842763

申请日：2001-04-27

申请人： Kazuya Arakawa ,  Motoki Takase ,  Tsuyoshi Muramatsu

发明人： Kazuya Arakawa ,  Motoki Takase ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/00

CPC分类号： G06F9/4494

摘要： A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.

摘要翻译： C元素控制流水线寄存器并连续传输数据包。 当死锁状态发生时，流水线寄存器中的数据包被主复位信号擦除，主机传输标志操作电路重写流水线寄存器中的数据包，使其具有位于“H”的主机传输标志， 级别，此后，当在后续阶段中检测到主机传输标志时，数据分组被传送到主机。

公开(公告)号：US06977756B2

公开(公告)日：2005-12-20

申请号：US09878394

申请日：2001-06-12

申请人： Takahiko Nakano ,  Motoki Takase ,  Tsuyoshi Muramatsu

发明人： Takahiko Nakano ,  Motoki Takase ,  Tsuyoshi Muramatsu

IPC分类号： G06T5/00 ,  G09G5/00 ,  H04N1/405 ,  G06K15/00

CPC分类号： H04N1/4052

摘要： A data driven type processing device has an error diffusion computing unit built therein. An error holding register is provided within the error diffusion computing unit, and is used to successively store and update a value of error information of a pixel that is to be diffused to a neighboring pixel being processed continuously. An error data memory is provided outside the computing unit, and is used to store and update a value of the error information that is to be diffused to another neighboring pixel being processed discontinuously. The error information and the values to be diffused are stored in a packet, and the packet is circulated for operation.

摘要翻译： 数据驱动型处理装置内置有误差扩散计算单元。 在误差扩散计算单元内提供误差保持寄存器，并且用于连续地存储和更新要被扩散的像素的错误信息的值连续地被连续处理的相邻像素。 在计算单元外部提供错误数据存储器，并且用于存储和更新要被扩散到正被不连续处理的另一个相邻像素的错误信息的值。 将错误信息和要扩散的值存储在分组中，并且分组被循环以进行操作。

公开(公告)号：US06525777B2

公开(公告)日：2003-02-25

申请号：US09326648

申请日：1999-06-07

申请人： Takeshi Kameda ,  Tsuyoshi Muramatsu

发明人： Takeshi Kameda ,  Tsuyoshi Muramatsu

IPC分类号： H04N546

CPC分类号： H04N5/46 ,  H04N21/443

摘要： A video signal processor includes a receiver unit receiving a broadcasted wave, an identify unit identifying a broadcasting system according to a signal received by the receiver unit, and a plurality of data driven processors processing a video signal received by the receiver unit according to the broadcasting system identified by the identify unit. Since the plurality of data driven processors process a video signal received by the receiver unit according to the broadcasting system identified by the identify unit, video data corresponding to the broadcasting system can be generated.

摘要翻译： 视频信号处理器包括：接收单元，接收广播波，识别单元，根据接收单元接收到的信号识别广播系统;以及多个数据驱动处理器，根据广播处理由接收机单元接收的视频信号 由识别单元识别的系统。 由于多个数据驱动处理器根据由识别单元识别的广播系统处理由接收器单元接收的视频信号，所以可以产生与广播系统对应的视频数据。

公开(公告)号：US5870620A

公开(公告)日：1999-02-09

申请号：US655460

申请日：1996-05-30

申请人： Ryuji Kadosumi ,  Tsuyoshi Muramatsu

发明人： Ryuji Kadosumi ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/82 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/4436

摘要： A data driven type information processor includes a firing control unit, an operation unit, and a program storage unit. The firing control unit sequentially receives data packets, and detects a data packet which stores paired data, and outputs the detected data packet. The operation unit receives a data packet output from the firing control unit, operates on the contents of the received data packet, stores the operation result in the received data packet, and outputs the received data packet. The program storage unit receives the data packet output from the operation unit, and reads a program word formed of a plurality of program word sets from a prestored data flow program by addressing based on the contents of the received data packet. Then, the program storage unit outputs no data packet if every Valid flag corresponding to each program word set in the read program word is invalid (data packet erasing), or generates a data packet corresponding to each of at least one program word set whose Valid flag is valid in the read program word, additionally stores data of the operation result in each generated data packet, and outputs each generated data packet (data packet copy). Consequently, data packet erasing or data packet copy by one addressing can be carried out on reading a program in the program storage unit.

摘要翻译： 数据驱动型信息处理器包括点火控制单元，操作单元和程序存储单元。 点火控制单元依次接收数据包，并检测存储配对数据的数据包，并输出检测到的数据包。 操作单元接收从点火控制单元输出的数据分组，对接收到的数据分组的内容进行操作，将操作结果存储在接收的数据分组中，并输出接收到的数据分组。 程序存储单元接收从操作单元输出的数据分组，并且通过基于所接收的数据分组的内容进行寻址，从预先存储的数据流程序读取由多个程序字集合形成的程序字。 然后，如果与读取的程序字中设置的每个程序字对应的每个有效标志无效（数据包擦除），则程序存储单元不输出数据包，或者生成对应于至少一个程序字集合的数据包 标志在读取程序字中有效，另外将操作结果的数据存储在每个生成的数据包中，并输出每个生成的数据包（数据包副本）。 因此，可以在读取程序存储单元中的程序时执行通过一个寻址的数据包擦除或数据包复制。

公开(公告)号：US5848290A

公开(公告)日：1998-12-08

申请号：US602422

申请日：1996-02-16

申请人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

发明人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/82 ,  G06F9/44

CPC分类号： G06F9/4436

摘要： In a system in which a plurality of data driven information processors are connected to each other to receive a data packet and to carry out processing simultaneously, each processor stores a processor number parameter ID of a data packet to be forcibly included in a specific data packet to be input. The forced input packet is a packet which each processor should receive and process unconditionally among packets addressed to the other processors excluding itself. The parameter ID is a number for identifying the other processors. Upon reception of an ordinary data packet, the processor compares information for specifying a processor to process the received ordinary data packet respectively with parameter ID and processor identification number PE# preassigned to each processor for identifying itself, and in response to matching between the information and any one of parameter ID and processor identification number PE#, takes in the received ordinary data packet in order to process the same. As a result, each processor can process not only a data packet to be processed in itself but also a data packet to be processed in the other processors, and a data transmission path among the processors can be set changeably according to the set parameter ID.

摘要翻译： 在其中多个数据驱动信息处理器彼此连接以接收数据分组并且同时执行处理的系统中，每个处理器存储要被强制包括在特定数据分组中的数据分组的处理器号码参数ID 被输入。 强制输入分组是一个分组，每个处理器应该在寻址到其他处理器之外的分组之间无条件地接收和处理其自身。 参数ID是用于识别其他处理器的数字。 在接收到普通数据包时，处理器比较用于指定处理器的信息以分别处理接收到的普通数据包的参数ID和处理器标识号PE＃，其被分配给每个处理器用于识别其自身，并且响应于信息与 参数ID和处理器识别号码PE＃中的任何一个，接收所接收的普通数据包以进行处理。 结果，每个处理器不仅可以处理本身要处理的数据分组，而且可以处理在其他处理器中要处理的数据分组，并且可以根据设置的参数ID可变地设置处理器之间的数据传输路径。

公开(公告)号：US5794064A

公开(公告)日：1998-08-11

申请号：US613671

申请日：1996-03-11

申请人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

发明人： Shinichi Yoshida ,  Tsuyoshi Muramatsu

IPC分类号： G06F15/82 ,  G06F9/44

CPC分类号： G06F9/4436

摘要： A data driven processor includes an output processing unit outputting a data packet outside the processor while referencing a branch control parameter register group. In the register group, a processor number/generation number specifying parameter P/G, a branch comparison parameter RM, and a branch comparison data parameter RD are stored. At the time of output of the data packet, the output processing unit reads out any one of a processor number and a generation number in the data packet according to parameter P/G, and sends out the data packet to any one of output ports OA and OB according to the result of predetermined operation processing using the read out number and parameters RM and RD. When a plurality of processors which operate as described above are connected to each other to carry out processing simultaneously while inputting/outputting a data packet, a data path among the processors can be set and changed easily according to any of the processor number and the generation number in the packet.

摘要翻译： 数据驱动处理器包括在参考分支控制参数寄存器组的同时在处理器外部输出数据分组的输出处理单元。 在寄存器组中，存储指定参数P / G，分支比较参数RM和分支比较数据参数RD的处理器编号/产生号。 在数据分组输出时，输出处理单元根据参数P / G读出数据分组中的处理器编号和生成编号中的任一个，并将数据分组发送到输出端口OA 和OB，根据使用读出数和参数RM和RD的预定操作处理的结果。 当如上所述操作的多个处理器彼此连接以在输入/输出数据分组时同时进行处理时，可以根据处理器编号和生成中的任何一个容易地设置和改变处理器之间的数据路径 数据包中的数字。

公开(公告)号：US5524112A

公开(公告)日：1996-06-04

申请号：US83281

申请日：1993-06-29

申请人： Daisuke Azuma ,  Tsuyoshi Muramatsu

发明人： Daisuke Azuma ,  Tsuyoshi Muramatsu

IPC分类号： G06F13/00 ,  G06F13/38 ,  H04J3/06 ,  H04L29/00 ,  H04L29/08 ,  H04L12/40 ,  H04J3/02

CPC分类号： H04J3/062

摘要： An interface device includes a data transmitter provided with a multiplexer for dividing k.times.n bits of data (k is an integer satisfying k.gtoreq.2) applied from a transmitting side data terminal equipment into k groups for time sequential output, and a data receiver provided with a data latch circuit for taking the first k-1 data groups transmitted from the data transmitter and a data latch circuit for taking the outputs from the k-1 data latch circuits and the last transmitted data group. In a period corresponding to one transmission, two data groups are supplied in time sequence from the data transmitter to the data receiver. There may be provided k data latch circuits so that the inputs of data latch circuit are all passed through the data latch circuits.

摘要翻译： 接口装置包括：数据发送器，具有多路复用器，用于将从发送侧数据终端设备应用的k×n位数据（k是满足k> / = 2的整数）划分成k组用于时间顺序输出;以及数据接收器， 具有用于获取从数据发送器发送的第一k-1个数据组的数据锁存电路和用于从k-1个数据锁存电路和最后发送的数据组获取输出的数据锁存电路。 在对应于一个传输的时段中，从数据发射机到数据接收机以时间顺序提供两个数据组。 可以提供k个数据锁存电路，使得数据锁存电路的输入全部通过数据锁存电路。