公开(公告)号：US20150048895A1

公开(公告)日：2015-02-19

申请号：US13965388

申请日：2013-08-13

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H03B28/00

CPC classification number: H03L1/028 ,  H03L1/02 ,  H03L1/026 ,  H03L7/06

Abstract: A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.

Abstract translation: 微机电系统（MEMS）振荡器提供具有与输出信号的预定频率不同的第一频率的振荡器输出信号。 误差判定电路基于初始频率偏移和/或温度从预定频率确定频率误差，并提供指示第一频率和预定频率之间的差的误差信息。 频率转换逻辑中的接收系统使用误差信息，该逻辑将振荡器输出信号用作频率参考。

公开(公告)号：US20140307759A1

公开(公告)日：2014-10-16

申请号：US14041459

申请日：2013-09-30

Applicant: Silicon Laboratories Inc.

Inventor： Siddharth Sundar ,  Michael J. Mills ,  Hua Zhu ,  Riad Wahby ,  Jeffrey L. Sonntag ,  Yunteng Huang ,  Anantha Nag Nemmani

IPC: H04B1/40 ,  H04B3/32

CPC classification number: H04B1/40 ,  H03M9/00 ,  H04B3/32

Abstract: A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels.

Abstract translation: 第一集成电路管芯从多个输入通道接收输入数据，并将来自多个输入通道的输入数据组合成组合数据。 第一集成电路管芯通过隔离通信通道传输组合的数据。 耦合到隔离通信信道的第二集成电路管芯对所发送的组合数据进行解码，并将经解码的发送的组合数据提供给对应于输入通道的各个输出通道。

公开(公告)号：US08786341B1

公开(公告)日：2014-07-22

申请号：US13833360

申请日：2013-03-15

Applicant: Silicon Laboratories Inc.

Inventor： Colin Weltin-Wu ,  Yunteng Huang

IPC: H03L7/06

CPC classification number: H03L7/1972 ,  H03L7/10

Abstract: A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.

Abstract translation: 数字频率合成器通过使用具有相位和频率路径的数字滤波器提供绝对锁相和较短的建立时间。 控制逻辑控制在频率采集期间禁用频率路径，并设置宽带宽。 在频率采集之后，使用输入时钟信号复位具有数字相位信息的计数器，使输出相位更接近与输入信号锁定，并且控制逻辑使数字环路滤波器中的相位路径能够实现较窄带宽的锁相 比起初始带宽。