公开(公告)号：US08860514B2

公开(公告)日：2014-10-14

申请号：US13724960

申请日：2012-12-21

Applicant: Silicon Laboratories Inc.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K3/02 ,  H03B5/30 ,  H03B19/00 ,  H03L1/02 ,  H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。

公开(公告)号：US10320509B2

公开(公告)日：2019-06-11

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04L7/033 ,  H04J3/14 ,  H04L12/24 ,  H04J3/06

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

公开(公告)号：US20160352506A1

公开(公告)日：2016-12-01

申请号：US14983830

申请日：2015-12-30

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H04L7/033 ,  H03L7/093 ,  H03L7/091 ,  H04L27/227 ,  H04J3/06

CPC classification number: H04L7/0332 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0994 ,  H04J3/0661 ,  H04L7/002 ,  H04L27/2272

Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

Abstract translation: 更具成本效益的漂移抖动滤波器利用偏移检测器，其接收第一信号和第二信号之间的定时差，并且如果定时差的大小高于预定阈值则提供第一调整量，否则提供第二调整量 零。 求和电路将定时差的大小调整第一或第二调整量。 环路滤波器接收求和电路输出并控制振荡器。 偏移检测器输出（根据定时差的幅度的第一调整值或零）被低通滤波，低通滤波被重新引入振荡器输出或反馈回路。 偏移检测器输出被累加并用于调整来自振荡器的反馈信号的相位。

公开(公告)号：US09621170B2

公开(公告)日：2017-04-11

申请号：US13965388

申请日：2013-08-13

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H03L7/099 ,  H03L7/02 ,  H03L1/02 ,  H03L7/06

CPC classification number: H03L1/028 ,  H03L1/02 ,  H03L1/026 ,  H03L7/06

Abstract: A micro electro mechanical system (MEMS) oscillator supplies an oscillator output signal having a first frequency that differs from a predetermined frequency of the output signal. An error determination circuit determines frequency error from the predetermined frequency based on initial frequency offset and/or temperature and provides the error information indicating a difference between the first frequency and the predetermined frequency. The error information is used by a receiving system in frequency translation logic that utilizes the oscillator output signal as a frequency reference.

公开(公告)号：US09118392B2

公开(公告)日：2015-08-25

申请号：US14041459

申请日：2013-09-30

Applicant: Silicon Laboratories Inc.

Inventor： Siddharth Sundar ,  Michael J. Mills ,  Hua Zhu ,  Riad Wahby ,  Jeffrey L. Sonntag ,  Yunteng Huang ,  Anantha Nag Nemmani

IPC: H04B1/38 ,  H04B1/40 ,  H04B3/32

CPC classification number: H04B1/40 ,  H03M9/00 ,  H04B3/32

Abstract: A first integrated circuit die receives input data from a plurality of input channels and combines the input data from the plurality of input channels into combined data. The first integrated circuit die transmits the combined data across an isolation communication channel. A second integrated circuit die that is coupled to the isolation communication channel decodes the transmitted combined data and supplies the decoded transmitted combined data to respective output channels corresponding to the input channels.

Abstract translation: 第一集成电路管芯从多个输入通道接收输入数据，并将来自多个输入通道的输入数据组合成组合数据。 第一集成电路管芯通过隔离通信通道传输组合的数据。 耦合到隔离通信信道的第二集成电路管芯对所发送的组合数据进行解码，并将经解码的发送的组合数据提供给对应于输入通道的各个输出通道。

公开(公告)号：US20140176201A1

公开(公告)日：2014-06-26

申请号：US13724960

申请日：2012-12-21

Applicant: SILICON LABORATORIES INC.

Inventor： Colin Weltin-Wu ,  Yunteng Huang ,  Manu Seth

IPC: H03K5/13

CPC classification number: H03K5/131

Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.

Abstract translation: 分数N分频器提供分频时钟信号。 在具有与分数N分频器的数字量化误差成线性比例的延迟的数字 - 时间转换器电路中产生经调整的分频时钟信号。 调整后的分频时钟信号基于充电到预定电平的第一和第二电容器产生。 第一和第二电容器的充电在分频时钟的交替周期中交错。 用对应于各个数字量化误差的电流对每个电容器的充电与固定电流进行充电。 响应于第一电容器充电到预定电压而产生经调整的分频时钟信号的第一脉冲的第一边缘，并且响应于第二电容器充电而产生经调整的分频时钟信号的下一脉冲的第一边沿 预定电压。

公开(公告)号：US10057051B2

公开(公告)日：2018-08-21

申请号：US14983830

申请日：2015-12-30

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H04L7/033 ,  H04L27/227 ,  H04J3/06 ,  H03L7/093 ,  H03L7/08 ,  H03L7/081 ,  H03L7/085 ,  H03L7/099

CPC classification number: H04L7/0332 ,  H03L7/0805 ,  H03L7/081 ,  H03L7/085 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/0994 ,  H04J3/0661 ,  H04L7/002 ,  H04L27/2272

Abstract: A more cost effective wander jitter filter utilizes an excursion detector that receives a timing difference between a first signal and a second signal and supplies a first adjustment amount if a magnitude of the timing difference is above a predetermined threshold and otherwise supplies a second adjustment amount of zero. A summing circuit adjusts a magnitude of the timing difference by the first or second adjustment amount. A loop filter receives the summing circuit output and controls an oscillator. The excursion detector output (first adjustment value or zero according to the magnitude of the timing difference) is low pass filtered and the low pass filtered is reintroduced into the oscillator output or the feedback loop. The excursion detector output is accumulated and used to adjust a phase of the feedback signal from the oscillator.

公开(公告)号：US09705668B2

公开(公告)日：2017-07-11

申请号：US14725053

申请日：2015-05-29

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H03D3/24 ,  H04L7/033 ,  H04L27/227

CPC classification number: H04L7/0332 ,  H03L7/0807 ,  H03L7/148 ,  H04J3/0614 ,  H04L27/2272

Abstract: A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.

公开(公告)号：US20170187481A1

公开(公告)日：2017-06-29

申请号：US14980036

申请日：2015-12-28

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang ,  Adam B. Eldredge ,  Gregory J. Richmond

IPC: H04J3/14 ,  H04J3/06 ,  H04L7/033 ,  H04L12/24

CPC classification number: H04J3/14 ,  H04J3/0688 ,  H04J3/0691 ,  H04L7/0331 ,  H04L41/0672

Abstract: Techniques for generating a fail safe clock signal improves reliability of one or more output clock signals generated based on one or more input clock signals and an internally generated reference clock signal. By continuously monitoring the frequencies of the one or more input clock signals and reducing or eliminating effects of any static frequency offset between multiple input clock signals, the fail safe clock generator can detect very small relative frequency changes between the inputs or within a particular input. By comparing the input clock frequencies against a reference clock signal frequency over time of a clock signal generated by an internal oscillator, the fail safe clock generator may further detect which one of multiple input clocks has frequency deviation. The fail safe clock generator uses an internal oscillator generating a reference clock signal having a short-term stable frequency.

公开(公告)号：US20160352505A1

公开(公告)日：2016-12-01

申请号：US14725053

申请日：2015-05-29

Applicant: Silicon Laboratories Inc.

Inventor： Yunteng Huang

IPC: H04L7/033 ,  H04L27/227

CPC classification number: H04L7/0332 ,  H03L7/0807 ,  H03L7/148 ,  H04J3/0614 ,  H04L27/2272

Abstract: A gap detector detects when a phase difference between a feedback signal and a clock signal is larger than a gap threshold. If the phase difference is larger than the gap threshold, then the phase difference is modified by subtracting a gap value from the phase difference. If the phase difference is less than the threshold, the phase difference is not modified. A loop filter receives and filters the modified or unmodified phase difference and controls an oscillator. An accumulator circuit accumulates the modified phase difference and supplies a phase adjust signal. A low pass filter receives the phase adjust signal and supplies a filtered phase adjust signal that is used to slowly adjust the output of the oscillator.

Abstract translation: 间隙检测器检测反馈信号和时钟信号之间的相位差何时大于间隙阈值。 如果相位差大于间隙阈值，则通过从相位差减去间隙值来修改相位差。 如果相位差小于阈值，则不会修改相位差。 环路滤波器接收并过滤修改或未修改的相位差并控制振荡器。 累加器电路累积修正的相位差并提供相位调整信号。 低通滤波器接收相位调整信号，并提供用于缓慢调整振荡器输出的滤波相位调整信号。