公开(公告)号：US11573730B2

公开(公告)日：2023-02-07

申请号：US17204067

申请日：2021-03-17

Applicant: Silicon Motion, Inc.

Inventor： An-Pang Li

IPC: G06F3/06

Abstract: A technology for controlling non-volatile memory with a multi-stage controller is shown. The multi-stage controller uses an upper on-chip interconnect and a lower on-chip interconnect and includes a serial peripheral bus (SPI) loader, a frond-end central processing unit (FE CPU), and an arbitrator. When being connected to the lower on-chip interconnect, the SPI loader performs code loading for the multi-stage controller. After the SPI loader finishes the code loading, the SPI loader is disconnected from the lower-stage on-chip bus, and the arbitrator connects the FE CPU to the lower on-chip interconnect. This way, the communication channel between the upper on-chip interconnect and the lower on-chip interconnect is not occupied by the FE CPU.

公开(公告)号：US20220121614A1

公开(公告)日：2022-04-21

申请号：US17071996

申请日：2020-10-15

Applicant: Silicon Motion, Inc.

Inventor： An-Pang Li

IPC: G06F15/167 ,  G06F15/78 ,  G06F13/40 ,  G06F13/16 ,  G06F13/38

Abstract: The present invention provides a SoC including a first CPU, a first tightly-coupled memory, a second CPU and a second tightly-coupled memory is disclosed. The first CPU includes a first core circuit, a first level one memory interface and a first level two memory interface. The first tightly-coupled memory is directly coupled to the first level one memory interface, and the first tightly-coupled memory includes a first mailbox. The second CPU includes a second core circuit, a second level one memory interface and a second level two memory interface. The second tightly-coupled memory is directly coupled to the second level one memory interface, and the second tightly-coupled memory includes a second mailbox. When the first CPU sends a command to the second mailbox within the second tightly-coupled memory, the second core circuit directly reads the command from the second mailbox, without going through the second level two memory interface.