公开(公告)号：US20200020789A1

公开(公告)日：2020-01-16

申请号：US16576370

申请日：2019-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

公开(公告)号：US20170338330A1

公开(公告)日：2017-11-23

申请号：US15494499

申请日：2017-04-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

IPC: H01L29/66 ,  H01L27/11521 ,  H01L21/3213

CPC classification number: H01L29/66825 ,  H01L21/32133 ,  H01L27/11521 ,  H01L29/42328

Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.