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    Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate
    1.
    发明授权
    Method of forming a semiconductor device with memory cells, high voltage devices and logic devices on a substrate 有权

    公开(公告)号：US11737266B2

    公开(公告)日：2023-08-22

    申请号：US17339880

    申请日：2021-06-04

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Guo Xiang Song ,  Chunming Wang ,  Leo Xing ,  Xian Liu ,  Nhan Do

    IPC: H01L27/088 ,  H10B41/41

    CPC classification number: H10B41/41

    Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.

    Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate
    5.
    发明申请
    Method Of Making Memory Cells, High Voltage Devices And Logic Devices On A Substrate 有权

    公开(公告)号：US20210398995A1

    公开(公告)日：2021-12-23

    申请号：US17129865

    申请日：2020-12-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Jack Sun ,  Chunming Wang ,  Xian Liu ,  Andy Yang ,  Guo Xiang Song ,  Leo Xing ,  Nhan Do

    IPC: H01L27/11531 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/423 ,  H01L29/66

    Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the first and second areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in the first and second areas, forming a protective layer in the first and second areas and then removing the second conductive layer from the third area, then forming blocks of conductive material in the third area, then etching in the first and second areas to form select and HV gates, and replacing the blocks of conductive material with blocks of metal material.

    Method of making split gate non-volatile flash memory cell
    6.
    发明授权
    Method of making split gate non-volatile flash memory cell 有权

    公开(公告)号：US10833178B2

    公开(公告)日：2020-11-10

    申请号：US16576370

    申请日：2019-09-19

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Leo Xing ,  Andy Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L27/11521 ,  H01L27/11531 ,  H01L29/66 ,  H01L21/3213 ,  H01L27/11536 ,  H01L29/423 ,  H01L49/02

    Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.

    Twin bit non-volatile memory cells with floating gates in substrate trenches
    7.
    发明授权
    Twin bit non-volatile memory cells with floating gates in substrate trenches 有权

    公开(公告)号：US10600794B2

    公开(公告)日：2020-03-24

    申请号：US16160812

    申请日：2018-10-15

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Chunming Wang ,  Andy Liu ,  Xian Liu ,  Leo Xing ,  Melvin Diao ,  Nhan Do

    IPC: H01L29/66 ,  H01L29/788 ,  H01L29/423 ,  H01L27/11521 ,  H01L27/11524 ,  H01L21/28

    Abstract: A twin bit memory cell includes first and second spaced apart floating gates formed in first and second trenches in the upper surface of a semiconductor substrate. An erase gate, or a pair of erase gates, are disposed over and insulated from the floating gates, respectively. A word line gate is disposed over and insulated from a portion of the upper surface that is between the first and second trenches. A first source region is formed in the substrate under the first trench, and a second source region formed in the substrate under the second trench. A continuous channel region of the substrate extends from the first source region, along a side wall of the first trench, along the portion of the upper surface that is between the first and second trenches, along a side wall of the second trench, and to the second source region.

    Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps
    8.
    发明授权
    Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps 有权

    公开(公告)号：US10217850B2

    公开(公告)日：2019-02-26

    申请号：US15474879

    申请日：2017-03-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  Chien-Sheng Su ,  Nhan Do ,  Chunming Wang

    IPC: H01L29/66 ,  H01L29/788 ,  H01L27/07 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28

    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).

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