公开(公告)号：US5367660A

公开(公告)日：1994-11-22

申请号：US241328

申请日：1994-05-11

申请人： Tal Gat ,  Simcha Gochman ,  Michael Kagan

发明人： Tal Gat ,  Simcha Gochman ,  Michael Kagan

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F13/00

CPC分类号： G06F12/0815 ,  G06F12/0859

摘要： An improved cache memory for use with a microprocessor. A line buffer which stores a tag and offset field and the corresponding line of data is employed. Valid bits are associated with different potions of the data stored in the line buffer. Thus during a line fill, by way of example, an instruction may be read from the line buffer before the entire line is filled from main memory.

摘要翻译： 用于微处理器的改进的高速缓冲存储器。 使用存储标签和偏移字段的行缓冲器以及相应的数据行。 有效位与存储在行缓冲区中的不同数量的数据相关联。 因此，在行填充期间，作为示例，可以在从主存储器填充整行之前从行缓冲器读取指令。

公开(公告)号：US5764932A

公开(公告)日：1998-06-09

申请号：US771529

申请日：1996-12-23

申请人： Simcha Gochman ,  Gil Stoler

发明人： Simcha Gochman ,  Gil Stoler

IPC分类号： G06F13/40 ,  G06F13/14 ,  G06F13/38

CPC分类号： G06F13/4027

摘要： To improve computer performance, a second processor can be added to a computer system. However, when a second processor is added to a computer system, a dual processing protocol is required to ensure that the two processors share the computer resources. A robust dual processing protocol is introduced that allows two processors to share a single processor bus in an efficient manner. The dual processing protocol allows pipelined bus transfers wherein partial control of the bus is transferred. Furthermore, the dual processing protocol ensures cache coherency by having any modified cache line written back to main memory when a memory location represent by a modified internal cache line is accessed. The dual processing Protocol is designed to support a well defined fair and robust arbitration DP protocol between two processors that is independent of the core frequency and the bus fraction ratio. As such, the dual processing protocol is functional even if the two processors are running with different bus fractions ("heterogeneous DP"). The dual processing protocol is a Pure Bus Clock based protocol such that all the indications on the private interface are in pure bus-clock domain. This enables running in high core frequency, while not affecting the board related private interface parameters (such as flight time, valid/setup/hold of the processors private pins)--which makes the protocol robust and applicable to future upgrades/products with much higher internal frequencies.

摘要翻译： 为了提高计算机性能，可以将第二处理器添加到计算机系统。 然而，当将第二处理器添加到计算机系统时，需要双重处理协议以确保两个处理器共享计算机资源。 引入了强大的双处理协议，允许两个处理器以有效的方式共享单个处理器总线。 双处理协议允许其中传送总线的部分控制的流水线总线传输。 此外，当通过修改的内部高速缓存行表示的存储器位置被访问时，双重处理协议通过将任何经修改的高速缓存行写回到主存储器来确保高速缓存一致性。 双处理协议被设计为支持独立于核心频率和总线分数比的两个处理器之间的良好定义的公平和可靠的仲裁DP协议。 因此，即使两个处理器以不同的总线部分（“异种DP”）运行，双重处理协议也是有效的。 双处理协议是基于纯总线时钟的协议，使得私有接口上的所有指示都处于纯总线时钟域。 这使得能够以高核心频率运行，同时不影响板级相关的专用接口参数（如飞行时间，处理器专用引脚的有效/设置/保持），这使得协议稳健且适用于将来升级/产品高得多 内部频率。