Testing multiple levels in integrated circuit technology development
    12.
    发明授权
    Testing multiple levels in integrated circuit technology development 失效
    在集成电路技术开发中测试多层次

    公开(公告)号:US06875560B1

    公开(公告)日:2005-04-05

    申请号:US10632471

    申请日:2003-08-01

    IPC分类号: G01R31/28 G03C5/00 H01L23/544

    摘要: A method of testing an integrated circuit is provided, which includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate and a first channel is formed in the first dielectric layer in contact with the semiconductor device. A first contact pad mask layer is formed and a first contact pad in the first contact pad mask layer is formed in contact with the first channel. The first contact pad is used to test the first channel and the semiconductor device and the first contact pad mask layer and the first contact pad are removed.

    摘要翻译: 提供一种测试集成电路的方法,其包括提供其上设置有半导体器件的半导体衬底。 在半导体衬底上形成第一电介质层,并且在与半导体器件接触的第一电介质层中形成第一沟道。 形成第一接触焊盘掩模层,并且第一接触焊盘掩模层中的第一接触焊盘形成为与第一通道接触。 第一接触焊盘用于测试第一通道,半导体器件和第一接触焊盘掩模层和第一接触焊盘被去除。