公开(公告)号：US20240345159A1

公开(公告)日：2024-10-17

申请号：US18683270

申请日：2022-07-08

申请人： TECHWIDU CO., LTD.

发明人： Hyoung-Rae KIM ,  Dong-Yul LEE ,  Jun-Hyung HA

IPC分类号： G01R31/3163 ,  G01R31/28

CPC分类号： G01R31/3163 ,  G01R31/2831

摘要： Provided is a test circuit configured to receive an inspection command from automatic test equipment (ATE) and test a device under test (DUT), and the test circuit includes a plurality of analog inspection circuits electrically connected to the DUT to test an operation thereof, and a digital control circuit configured to control operations of the analog inspection circuits, wherein the digital control circuit and the analog inspection circuits are located apart from each other.

公开(公告)号：US20240345135A1

公开(公告)日：2024-10-17

申请号：US18299711

申请日：2023-04-12

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Tien Yu CHEN

IPC分类号： G01R1/44 ,  G01R31/28

CPC分类号： G01R1/44 ,  G01R31/2831

摘要： A preheating control system comprising a testing device and a processor is provided in present disclosure. The testing device is configured to perform a wafer testing on a wafer lot and perform a device preheating on the testing device. The processor is coupled to the testing device and comprises a timing circuit and a controlling circuit. The timing circuit is configured to calculate a lot-changing time, wherein the lot-changing time is a difference between a time corresponding to removal of a previous wafer lot from the testing device and a time corresponding to insertion of the wafer lot into the testing device. The controlling circuit is configured to control the testing device to perform the wafer testing, and configured to control the testing device to perform the device preheating according to the lot-changing time and a standard lot-changing time.

公开(公告)号：US12107019B2

公开(公告)日：2024-10-01

申请号：US17000528

申请日：2020-08-24

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Shun Hirao

IPC分类号： G06F17/18 ,  G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  G06F11/00

CPC分类号： H01L22/20 ,  G01R31/2831 ,  G01R31/318511 ,  G06F17/18 ,  G06F11/008 ,  H01L22/00

摘要： According to an embodiment, an information processing apparatus includes one or more processors. The processors are configured to: generate a plurality of shuffle maps obtained by randomly shuffling, from positions to others, at least some of subject values contained in a subject map having the subject values arrayed in N dimensions (N is an integer of 1 or more); generate a subject vector expressing features of a frequency domain of the subject map and random vectors expressing features of respective frequency domains of the shuffle maps; and derive, as an evaluation value for whether the subject map has a random characteristic, a testing result of statistical hypothesis testing on feature differences between the subject vector and the respective random vectors.

公开(公告)号：US20240321653A1

公开(公告)日：2024-09-26

申请号：US18613122

申请日：2024-03-22

申请人： WALTON ADVANCED ENGINEERING, INC.

发明人： HONG-CHI YU ,  CHUN-JUNG LIN ,  RUEI-TING GU

IPC分类号： H01L21/66 ,  G01R31/28 ,  H01L23/00

CPC分类号： H01L22/32 ,  G01R31/2831 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/03464 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/48105 ,  H01L2224/48227

摘要： A wafer package for protection of an aluminum die pad of a die from damages during probe testing process is provided. Before performing the probe testing process on a plurality of dies of the wafer package, at least one bump is disposed on a surface of the aluminum die pad of the die of the wafer package by electroless plating. The bump is a metal stack structure having a certain thickness and composed of a nickel layer and a gold layer stacked over the aluminum die pad in turn, or a nickel layer, a palladium layer, and a gold layer stacked over the aluminum die pad in turn. Thus structural strength of the aluminum die pad of the die is increased to prevent damages during the probe testing process. Therefore, quality and reliability of the dies in following operations such as wire bonding are increased.

公开(公告)号：US20240319259A1

公开(公告)日：2024-09-26

申请号：US18608292

申请日：2024-03-18

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Minseok KIM ,  Taesin KWAG ,  Yeonjeong KIM ,  Hyungkeun YOO ,  Jongchul KIM ,  Kyunghoon LEE

IPC分类号： G01R31/28 ,  G06F30/367 ,  G06T7/00

CPC分类号： G01R31/2831 ,  G06F30/367 ,  G06T7/0004 ,  G06T2207/30148

摘要： Provided is an electrical reliability properties prediction method including generating a plurality of pieces of optical spectrum data of a substrate, performing a wafer level reliability (WLR) process on the substrate, measuring electrical reliability property data based on the WLR process, matching an inspection region to the plurality of pieces of optical spectrum data and the electrical reliability property data, generating a data set, performing data pre-processing, training an electrical reliability properties prediction model, acquiring a plurality of pieces of target optical data from a database, and extracting, with respect to the plurality of pieces of target optical data, a feature vector from the plurality of pieces of target optical data, and detecting predicted electrical reliability property data of the plurality of pieces of target optical data based on the feature vector.

公开(公告)号：US12085601B2

公开(公告)日：2024-09-10

申请号：US17568278

申请日：2022-01-04

申请人： STMicroelectronics S.r.l.

发明人： Romeo Letor ,  Veronica Puntorieri

IPC分类号： G01R31/26 ,  G01R19/165 ,  G01R19/32 ,  G01R31/28

CPC分类号： G01R31/2642 ,  G01R19/16528 ,  G01R19/32 ,  G01R31/2831 ,  G01R31/2884 ,  G01R31/2886 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/14

摘要： A system to monitor a MOSFET, the system including a switching arrangement configured to switchably isolate a gate terminal of the MOSFET and a source terminal of the MOSFET from a gate-control voltage source and a test circuit configured to detect a change in a gate-to-source voltage of the MOSFET over a test period, the test period occurring while the gate terminal and the source terminal are isolated.

公开(公告)号：US12050245B2

公开(公告)日：2024-07-30

申请号：US17664771

申请日：2022-05-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kong-Beng Thei ,  Jung-Hui Kao ,  Jing-Jung Huang ,  Fu-Hsiung Yang

IPC分类号： G01R31/28

CPC分类号： G01R31/2831 ,  G01R31/2884

摘要： A plurality of devices for testing, connected in series using one or more redistribution layers (RDLs), are used to perform a semiconductor device test on a plurality of dies. As a result, the semiconductor device test may support thousands of gross dies per wafer or greater (e.g., 10,000 dies or greater). Furthermore, the RDL(s) may be removed after use. In some implementations, the devices for testing corresponding to the dies may execute the semiconductor device test sequentially. Accordingly, test data may be generated and may include a bit sequence, where a first bit in the bit sequence indicates an overall outcome for the test and one or more subsequent bits in the bit sequence indicate respective outcomes for each semiconductor dies or for each line of the semiconductor device test.

公开(公告)号：US12032015B1

公开(公告)日：2024-07-09

申请号：US18055762

申请日：2022-11-15

申请人： Amazon Technologies, Inc.

发明人： Ilan Strulovici

IPC分类号： G01R31/28 ,  H01L21/66

CPC分类号： G01R31/2851 ,  G01R31/2831 ,  G01R31/2834 ,  G01R31/2884 ,  G01R31/2886 ,  H01L22/34 ,  H01L2924/00 ,  H01L2924/0002

摘要： Flexible input/output (I/O) allocation techniques for integrated circuit scan testing are disclosed. The techniques implement configurable definition of the core circuitry blocks comprising the scan domain under test and their mapping to the scan test pads. Scan testing of the scan domain is performed by receiving a test pattern on the set of one or more scan-in test pads, transmitting the test pattern to the scan domain via the set of one or more scan input channels, receiving a test response on the set of one or more scan output channels, and transmitting the test response to the set of one or more scan-out test pads.

公开(公告)号：US20240038600A1

公开(公告)日：2024-02-01

申请号：US18272126

申请日：2022-05-10

申请人： SHANGHAI ASPIRING SEMICONDUCTOR EQUIPMENT CO., LTD.

发明人： Chongji HUANG ,  Weiwei ZHAO ,  Puxi ZHOU

IPC分类号： H01L21/66 ,  G01R31/28 ,  G01R31/26

CPC分类号： H01L22/14 ,  H01L22/12 ,  G01R31/2831 ,  G01R31/2603

摘要： A measuring method and device based on the second harmonic for the whole area measurement of a wafer comprises three modes: a fixed-point measurement, a scanning measurement, and a combination of the fixed-point measurement and the scanning measurement. The scanning measurement solution measures the entire wafer under the premise of ensuring high measurement efficiency, obtain the position, size and relative density distribution of electrical defects, and achieve locating and checking of abnormal points on the wafer. A new formula system is provided for describing the second harmonic signal, so that the actual measurement results and the theoretical model are unified under the three modes of the fixed-point measurement, the scanning measurement, and the combination of fixed-point measurement and scanning measurement, so that the second harmonic metrology technology is no longer only a qualitative analysis method, but also a quantitative analysis method.

公开(公告)号：US20240027518A1

公开(公告)日：2024-01-25

申请号：US17813934

申请日：2022-07-21

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ching-Chung WANG

IPC分类号： G01R31/28

CPC分类号： G01R31/2834 ,  G01R31/2831

摘要： The present disclosure provides a wafer testing method, including: assigning multiple testing programs to multiple wafers, wherein each of the testing programs includes testing algorithms configured to measure parameters of the wafers; setting multiple sets of testing conditions for the testing programs; and testing at least one of the wafers by executing a corresponding one of the testing programs according to a corresponding one of the testing conditions.