Lane adaptation in high-speed serial links

    公开(公告)号:US11177986B1

    公开(公告)日:2021-11-16

    申请号:US17205456

    申请日:2021-03-18

    Abstract: Adaptive equalizer circuitry including both a continuous time equalizer (CTE) and a discrete time equalizer (DTE) and a method of jointly adapting the CTE and DTE in lane adaptation. Jointly adaptation of the CTE and DTE is performed by adapting the DTE at each of a plurality of filter characteristic settings of the CTE and determining a figure of merit for signals filtered by the CTE and DTE at that condition. Adaptation of the DTE may be performed by dynamically adjusting a convergence coefficient based on a history of error gradients. After a figure of merit is determined for each of the plurality of CTE filter characteristics, a CTE filter characteristic setting is then selected based on those figure of merit values, for example at a CTE setting near a midpoint of an acceptable region of figure of merit values.

    EQUALIZER ADAPTATION FOR DATA LINK
    14.
    发明公开

    公开(公告)号:US20240146584A1

    公开(公告)日:2024-05-02

    申请号:US18049865

    申请日:2022-10-26

    CPC classification number: H04L25/03076

    Abstract: A method for adapting a continuous time equalizer (CTE) includes determining a gain of a discrete time equalizer (DTE) and determining whether the gain has increased or decreased by more than the threshold amount. Responsive to determining that the gain has increased or decreased by more than the threshold amount, the method includes sequentially configuring the CTE for multiple CTE settings such that gain of the CTE is caused to increase or decrease in a same direction with the change in gain of the DTE. The method also includes determining a separate figure of merit (FOM) for each of the multiple CTE settings and selecting a new CTE setting from the multiple CTE settings based on the FOM for each of the multiple CTE settings.

    Systems and Methods for Programming Electrical Fuse

    公开(公告)号:US20220229961A1

    公开(公告)日:2022-07-21

    申请号:US17411262

    申请日:2021-08-25

    Abstract: A system for programming an eFuse array in an integrated circuit (IC) includes an eFuse data file which has a first plurality of bits. The system includes a data compression module which has an input coupled to receive the eFuse data file. The data compression module reduces the size of the eFuse data file and provides a compressed data file. The compressed data file has fewer bits than the eFuse data file. The system includes an eFuse controller which has an input coupled to receive the compressed data file. The eFuse controller programs the eFuse array to permanently store the compressed data file in the eFuse array.

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