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公开(公告)号：US12074607B2
公开(公告)日：2024-08-27
申请号：US17825864
申请日：2022-05-26
发明人： Narasimhan Rajagopal , Nithin Gopinath , Viswanathan Nagarajan , Neeraj Shrivastava , Visvesvaraya A. Pentakota , Harshit Moondra , Abhinav Chandra
IPC分类号： H03M1/10
CPC分类号： H03M1/1014
摘要： A circuit includes a nonlinear analog-to-digital converter (ADC) configured to provide a first digital output based on an analog input signal. The circuit also includes a linearization circuit having a lookup table (LUT) memory configured to store initial calibration data. The linearization circuit is coupled to the nonlinear ADC and is configured to: determine updated calibration data based on the initial calibration data; replace the initial calibration data in the LUT memory with the updated calibration data; and provide a second digital output at a linearization circuit output of the linearization circuit based on the first digital output and the updated calibration data.
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公开(公告)号：US10930362B2
公开(公告)日：2021-02-23
申请号：US16916911
申请日：2020-06-30
发明人： Aravind Ganesan , Jaiganesh Balakrishnan , Nagarajan Viswanathan , Yeswanth Guntupalli , Ajai Paulose , Mathews John , Jagannathan Venkataraman , Neeraj Shrivastava
摘要： A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.
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公开(公告)号：US10181861B1
公开(公告)日：2019-01-15
申请号：US15883623
申请日：2018-01-30
IPC分类号： H03M1/36 , H03K19/0175
摘要： A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.
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公开(公告)号：US20170302287A1
公开(公告)日：2017-10-19
申请号：US15485552
申请日：2017-04-12
发明人： Srinivas Kumar Reddy Naru , Visvesvaraya Pentakota Appala , Shagun Dusad , Neeraj Shrivastava , Viswanathan Nagarajan , Ani Xavier , Rishi Soundararajan , Sai Aditya Nurani , Roswald Francis
CPC分类号： H03M1/06 , H03M1/1038 , H03M1/109 , H03M1/1205 , H03M1/164 , H03M1/361
摘要： The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.
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公开(公告)号：US09548752B1
公开(公告)日：2017-01-17
申请号：US15048027
申请日：2016-02-19
发明人： Neeraj Shrivastava , Supreet Joshi , Himanshu Varshney , Jafar Sadique Kaviladath , Visvesvaraya Pentakota , Shagun Dusad
CPC分类号： H03M1/1009 , H03M1/1019 , H03M1/1057 , H03M1/66 , H03M1/742 , H03M1/745 , H03M1/785
摘要： The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.
摘要翻译： 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。
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公开(公告)号：US11881867B2
公开(公告)日：2024-01-23
申请号：US17467561
申请日：2021-09-07
发明人： Narasimhan Rajagopal , Eeshan Miglani , Chirag Chandrahas Shetty , Neeraj Shrivastava , Shagun Dusad , Srinivas Kumar Reddy Naru , Nithin Gopinath , Charls Babu , Shivam Srivastava , Viswanathan Nagarajan , Jagannathan Venkataraman , Harshit Moondra , Prasanth K , Visvesvaraya Appala Pentakota
IPC分类号： H03M1/10
CPC分类号： H03M1/1019
摘要： In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.
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公开(公告)号：US20230344436A1
公开(公告)日：2023-10-26
申请号：US17729374
申请日：2022-04-26
IPC分类号： H03M1/06
CPC分类号： H03M1/0641 , H03M1/0626
摘要： An analog-to-digital converter circuit module utilizing dither to reduce multiplicative noise. A dither generation circuit generates a noise-shaped analog dither signal having lower amplitudes at frequencies below a cutoff frequency than at frequencies above the cutoff frequency. The noise-shaped analog dither signal is added to the input analog signal to be converted and the summed signal applied to an analog-to-digital converter The dither generation circuit may be implemented as an analog dither generator followed by an analog high-pass filter. The dither generation circuit may alternatively be implemented digitally, for example with a digital noise-shaping filter applying a high-pass digital filter to a pseudo-random binary sequence. The digital dither generation circuit may alternatively be implemented by one or more 1-bit sigma-delta modulators, each generating a bit of a digital dither sequence that is converted to analog.
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公开(公告)号：US10396814B2
公开(公告)日：2019-08-27
申请号：US16211259
申请日：2018-12-06
IPC分类号： H03M1/36 , H03K19/0175
摘要： A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.
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公开(公告)号：US11438001B2
公开(公告)日：2022-09-06
申请号：US17133745
申请日：2020-12-24
发明人： Narasimhan Rajagopal , Chirag Chandrahas Shetty , Neeraj Shrivastava , Prasanth K , Eeshan Miglani
摘要： A method of using an analog-to-digital converter system includes receiving a sampled voltage corresponding to one of an input voltage and a known voltage, causing preamplifiers to generate output signals based on the sampled voltage, generating first and second signals based on the output signals, causing a delay-resolving delay-to-digital backend to generate a single-bit digital signal representing an order of receipt of the first and second signals, and adjusting one or more of the preamplifiers based on the digital signal. The disclosure also relates to a system which includes a voltage-to-delay frontend and a delay-resolving backend, and to a method which includes causing a delay comparator to generate a single-bit digital signal representing an order of receipt of input signals, causing the comparator to transmit a residue delay signal to a succeeding comparator, and transmitting a signal to adjust one or more of the preamplifiers based on the digital signal.
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公开(公告)号：US20220247421A1
公开(公告)日：2022-08-04
申请号：US17588493
申请日：2022-01-31
发明人： Visvesvaraya Appala Pentakota , Srinivas Kumar Reddy Naru , Chirag Shetty , Eeshan Miglani , Neeraj Shrivastava , Narasimhan Rajagopal , Shagun Dusad
IPC分类号： H03M1/10
摘要： In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.
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