公开(公告)号：US20240184846A1

公开(公告)日：2024-06-06

申请号：US18129589

申请日：2023-03-31

Applicant: Texas Instruments Incorporated

Inventor： Mathews John ,  Pankaj Gupta ,  Jawaharlal Tangudu ,  Pankaj Gaur ,  Shikhar Chouhan ,  Manchi Sankalkar Ajay

IPC: G06F17/16

CPC classification number: G06F17/16

Abstract: An example apparatus includes: programmable circuitry to receive an input signal, a digital pre-distorter (DPD) output signal, and a power amplifier (PA) feedback signal; populate a partial matrix with a threshold number of rows of equation terms; compute a respective observation terms for each row in the threshold number of rows; reduce the partial matrix into a Hermitian matrix and reduce the observation terms into a vector; accumulate the Hermitian matrix and the vector onto the memory; regularize, after a determination that a threshold number of Hermitian matrices have been accumulated, the memory to form an output matrix; and pre-distort the input signal using the output matrix.

公开(公告)号：US20240356496A1

公开(公告)日：2024-10-24

申请号：US18615831

申请日：2024-03-25

Applicant: Texas Instruments Incorporated

Inventor： Pankaj Gupta ,  Jawaharlal Tangudu ,  Manchi Sankalkar Ajay ,  Mathews John ,  Jaiganesh Balakrishnan ,  Neeraj Kumar Sharma

IPC: H03F1/32

CPC classification number: H03F1/3247

Abstract: An example apparatus includes: memory having a terminal, the memory to store machine-readable instructions and adjacent channel leakage data; and programmable circuitry having a terminal coupled to the terminal of the memory, the programmable circuitry to execute the machine-readable instructions to: determine a range of out-of-band frequencies responsive to adjacent channel leakage ratio data; generate weight values responsive to electromagnetic emissions within the range of out-of-band frequencies of a first signal; modify a pre-distortion function responsive to the weight values; and apply the modified pre-distortion function to generate a second signal, the second signal to exhibit fewer emissions in the range of out-of-band frequencies than the first signal during transmission.

公开(公告)号：US20240143282A1

公开(公告)日：2024-05-02

申请号：US17977813

申请日：2022-10-31

Applicant: Texas Instruments Incorporated

Inventor： Mathews John ,  Jawaharlal Tangudu ,  Pankaj Gaur ,  Divyansh Jain ,  Pankaj Gupta

IPC: G06F7/57 ,  G06F17/16

CPC classification number: G06F7/57 ,  G06F17/16

Abstract: In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.

公开(公告)号：US20240297621A1

公开(公告)日：2024-09-05

申请号：US18592045

申请日：2024-02-29

Applicant: Texas Instruments Incorporated

Inventor： Jawaharlal Tangudu ,  Goutham Ramesh ,  Sarma Sundareswara Gunturi ,  Harsh Garg ,  Jaiganesh Balakrishnan ,  Mathews John ,  Sashidharan Venkatraman ,  Sanjay Pennam

IPC: H03F1/32 ,  H03F3/21

CPC classification number: H03F1/3241 ,  H03F3/21 ,  H03F2201/3233

Abstract: An example method includes switching a first multiplexer circuit associated with first delay circuitry from (a) a first sub-lookup table (LUT) of a first LUT of digital pre-distortion (DPD) corrector circuitry to (b) a first corresponding sub-LUT of a second LUT of the DPD corrector circuitry, the first sub-LUT associated with the first delay circuitry, the second LUT storing updated values to compensate for non-linearity of power amplifier circuitry of a transmitter including the DPD corrector circuitry. The method includes, based on a value of a counter being equal to a difference between (1) a first delay of the first delay circuitry and (2) a second delay of second delay circuitry, switching a second multiplexer circuit associated with the second delay circuitry from (a) a second sub-LUT of the first LUT to (b) a second corresponding sub-LUT of the second LUT, the second sub-LUT associated with the second delay circuitry.

公开(公告)号：US10930362B2

公开(公告)日：2021-02-23

申请号：US16916911

申请日：2020-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/18 ,  G11C17/16 ,  G11C17/14

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.

公开(公告)号：US10741268B2

公开(公告)日：2020-08-11

申请号：US16235698

申请日：2018-12-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aravind Ganesan ,  Jaiganesh Balakrishnan ,  Nagarajan Viswanathan ,  Yeswanth Guntupalli ,  Ajai Paulose ,  Mathews John ,  Jagannathan Venkataraman ,  Neeraj Shrivastava

IPC: G11C29/02 ,  G11C17/14 ,  G11C17/16 ,  G11C17/18

Abstract: A one-time write, read-only memory for storing trimming parameters includes an address pointer table, a fixed packet portion, and a flexible packet portion. The fixed packet portion includes one or more fixed packets, each fixed packet including trimming parameters for a component identified for trimming during a design phase. The flexible packet portion includes one or more flexible packets of different types. Each flexible packet includes trimming parameters for a component identified for trimming after the design phase. One packet type includes a length section and a number of fields equal to a value stored in the length section. Each field includes an address, a trimming parameter, and a mask. Another packet type includes trimming parameters associated with operands in operating instructions for a microcontroller, where the operands include an address and a mask.