公开(公告)号：US10591540B2

公开(公告)日：2020-03-17

申请号：US15925200

申请日：2018-03-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US09952283B2

公开(公告)日：2018-04-24

申请号：US14944971

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G06F11/00 ,  G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US20160069958A1

公开(公告)日：2016-03-10

申请号：US14944971

申请日：2015-11-18

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Rubin A. Parekhji ,  Arvind Jain ,  Sundarrajan Subramanian

IPC: G01R31/3177

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

公开(公告)号：US09091729B2

公开(公告)日：2015-07-28

申请号：US14487538

申请日：2014-09-16

Applicant: Texas Instruments Incorporated

Inventor： Prakash Narayanan ,  Arvind Jain ,  Sundarrajan Subramanian ,  Rubin A. Parekhji

IPC: G06F11/00 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318547

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.

Abstract translation: 电子扫描电路包括解压缩器（510），由解压缩器（510）馈送的多个扫描链（520.i），耦合到多个扫描链（520.i）以扫描的扫描电路（502,504） 由扫描链（520.i）馈送的掩蔽电路（590）和耦合到屏蔽电路（590）的可扫描屏蔽鉴定电路（550,560,580），屏蔽鉴定电路（550） ，560,580）以及扫描链（520.i）的扫描以及可扫描掩蔽鉴定电路（550,560,580）可扫描由解压缩器（510）的位的扫描，以及可扫描掩蔽鉴定电路（550,560,580） 通过屏蔽电路扫描扫描链（590）后扫描位。 还公开了其它扫描电路，处理，电路，装置和系统。